參數(shù)資料
型號(hào)： AD5321BRM
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 9/24頁(yè)
文件大小： 0K
描述： IC DAC 12BIT 2.5V 2-WIRE 8-MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 50
設(shè)置時(shí)間： 8µs
位數(shù)： 12
數(shù)據(jù)接口： I²C，串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 1.4mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 125k
AD5301/AD5311/AD5321
Rev. B | Page 17 of 24
POWER-DOWN MODES
The AD5301/AD5311/AD5321 have very low power consump-
tion, dissipating typically 0.36 mW with a 3 V supply and 0.75 mW
with a 5 V supply. Power consumption can be further reduced
when the DAC is not in use by putting it into one of three
power-down modes, which are selected by Bit 13 and Bit 12 (PD1
and PD0) of the control word. Table 6 shows how the state of
the bits corresponds to the mode of operation of the DAC.
Table 6. PD1 and PD0 Operating Modes
PD1
PD0
Operating Mode
0
Normal operation
0
1
Power-down (1 kΩ load to GND)
1
0
Power-down (100 kΩ load to GND)
1
Power-down (three-state output)
The software power-down modes programmed by PD1 and
PD0 may be overridden by the PD pin on the 8-lead version.
Taking this pin low puts the DAC into three-state power-down
mode. If PD is not used, tie it high.
When both bits are set to 0, the DAC works normally with its
normal power consumption of 150 μA at 5 V, while for the three
power-down modes, the supply current falls to 200 nA at 5 V
(50 nA at 3 V). Not only does the supply current drop, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode and provides a defined input
condition for whatever is connected to the output of the DAC
amplifier. There are three different options. The output is con-
nected internally to GND through a 1 kΩ resistor, a 100 kΩ
resistor, or it is left three-stated. Resistor tolerance = ±20%.
The output stage is illustrated in Figure 35.
REGISTER
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
0
092
7-
03
3
Figure 35. Output Stage During Power-Down
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
DAC register are unchanged when in power-down. The time to
exit power-down is typically 2.5 μs for VDD = 5 V and 6 μs when
VDD = 3 V (see Figure 21).
相關(guān)PDF資料
PDF描述
AD5322BRM IC DAC 12BIT DUAL R-R OUT 10MSOP
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