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參數(shù)資料
| 型號(hào)： | AD5323BRU |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/28頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12 BIT DUAL R-R 16-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 2.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 125k |
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AD5303/AD5313/AD5323
Rev. B | Page 15 of 28
FUNCTIONAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8-/10-/12-bits
respectively. They contain reference buffers and output buffer
amplifiers, and are written to via a 3-wire serial interface. They
operate from single supplies of 2.5 V to 5.5 V and the output
buffer amplifiers provide rail-to-rail output swing with a slew
rate of 0.7 V/μs. Each DAC is provided with a separate reference
input, which may be buffered to draw virtually no current from
the reference source, or unbuffered to give a reference input
range from GND to VDD. The devices have three programmable
power-down modes, in which one or both DACs may be turned
off completely with a high impedance output, or the output may
be pulled low by an on-chip resistor.
DIGITAL-TO-ANALOG
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 29 shows a block diagram of the
DAC architecture. Because the input coding to the DAC is
straight binary, the ideal output voltage is given by
N
REF
OUT
D
V
2
×
=
where:
D is the decimal equivalent of the binary code, which is loaded
to the DAC register:
0 to 255 for AD5303 (8 bits)
0 to 1023 for AD5313 (10 bits)
0 to 4095 for AD5323 (12 bits)
N is the DAC resolution.
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
OUTPUT BUFFER
AMPLIFIER
REFERENCE
BUFFER
SWITCH
CONTROLLED
BY CONTROL
LOGIC
VREFA
VOUTA
00
47
2
-02
9
Figure 29. Single DAC Channel Architecture
RESISTOR STRING
The resistor string section of the AD5303/AD5313/AD5323
is shown in Figure 30. It is simply a string of resistors, each of
value R. The digital code loaded to the DAC register determines
at what node on the string the voltage is tapped off to be fed
into the output amplifier. The voltage is tapped off by closing
one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
R
TO OUTPUT
AMPLIFIER
0
04
72-
030
Figure 30. Resistor String
DAC REFERENCE INPUTS
There is a reference input pin for each of the two DACs. The
reference inputs are buffered, but can also be configured as
unbuffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as GND and as high as VDD since there is no
restriction due to headroom and footroom of the reference
amplifier.
If there is a buffered reference in the circuit (for example,
REF192), there is no need to use the on-chip buffers of the
AD5303/AD5313/AD5323. In unbuffered mode, the input
impedance is still large at typically 180 kΩ per reference input
for 0 V to VREF mode and 90 kΩ for 0 V to 2 VREF mode.
The buffered/unbuffered option is controlled by the BUF A
and BUF B pins. If a BUF pin is tied high, the reference input
is buffered; if tied low, it is unbuffered.
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail, which gives an output
range of 0.001 V to VDD 0.001 V when the reference is VDD.
It is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 17.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5323BRU-REEL | 制造商:Analog Devices 功能描述:DAC 2-CH Resistor-String 12-bit 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:DAC 2CH RES-STRING 12-BIT 16TSSOP - Tape and Reel |
| AD5323BRU-REEL7 | 功能描述:IC DAC 12BIT SRL 16TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類(lèi)型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5323BRUZ | 功能描述:IC DAC 12BIT DUAL R-R 16-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類(lèi)型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF) |
| AD5323BRUZ | 制造商:Analog Devices 功能描述:D/A CONVERTER (D-A) IC |
| AD5323BRUZ1 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2.5 V to 5.5 V, 230 ??A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs |
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