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參數(shù)資料
| 型號(hào)： | AD5324 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | +2.5V to+5.5V,500μA, Quad Rail-to-Rail,Voltage Output 12-Bit DACs(滿幅度電壓輸出四12位D/A轉(zhuǎn)換器) |
| 中文描述： | 2.5V至5.5V，500μA，四軌至軌電壓輸出12位DAC（滿幅度電壓輸出四12位的D / A轉(zhuǎn)換器） |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | AD5324 |
–8–
AD5304/AD5314/AD5324 Prelimnary Technical Data
REV. PrE
TECHNCAL
SE RIAL INT E RFACE
T he AD5304/AD5314/AD5324 are controlled over a
versatile, 3-wire serial interface, which operates at
clock rates up to 30MHz and is compatible with
SPI
T M
, QSPI
T M
, MICROWIRE
T M
and DSP interface
standards.
Input Shift Register
T he input shift register is 16-bits wide. Data is loaded
into the device as a 16-bit word under the control of a
serial clock input, SCLK . T he timing diagram for this
operation is shown in Figure 1 on page 3. T he 16-bit
word consists of four control bits followed by 8, 10 or
12 bits of DAC data, depending on the device type.
T he first two bits loaded are the Bit 15 (MSB) and Bit
14. T hese determine whether the data is for DAC A,
DAC B, DAC C or DAC D. Bit 13 is
PD
which de-
termines whether the part is in Normal or Power-
Down mode. Bit 12 is
LDAC
which controls when
DAC registers and outputs are updated. Bits 13 and 12
control the operating mode of the DAC.
T ABLE 1. ADDRE SS BIT S FOR T HE AD53X 4
A1
A0
DAC Addressed
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
Figure 6. AD5304 Input Shift Register Contents
Figure 7. AD5314 Input Shift Register Contents
MSB
LSB
A1
PD LDAC D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
Data Bits
A0
MSB
LSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
Data Bits
A1
PD LDAC
A0
Address and C ontrol bits
PD
:
0: All four DACs go into Power-Down mode
consuming only 200nA @ 5V. T he DAC out-
puts enter a high-impedance state.
1:Normal operation.
LDAC
: 0:All four DAC registers and hence all DAC
outputs updated simultaneously on comple-
tion of the write sequence.
1: Addressed input register only is updated. T here
is no change in the contents of the DAC registers.
T he AD5324 uses all 12 bits of DAC data, the AD5314
uses 10 bits and ignores the two LSBs. T he AD5304 uses
8 bits and ignores the last 4 bits. T he data format is
straight binary, with all zeros corresponding to 0V output
and all ones corresponding to full-scale output (V
REF
-
1L SB).
T he
SYNC
input is a level-triggered input that acts as a
frame synchronization signal and chip enable. Data can
only be transferred into the device whilst
SYNC
is low.
T o start the serial data transfer,
SYNC
should be taken
low observing the minimum
SYNC
to SCLK active edge
setup time, t
4
. After
SYNC
goes low, serial data will be
shifted into the device's input shift register on the falling
edges of SCLK for 16 clock pulses. Any data and clock
pulses after the 16th falling edge of SCLK will be ignored
because the SCLK and DIN input buffers are powered
down. No further serial data transfer will occur until
SYNC
is taken high and low again.
Figure 8. AD5324 Input Shift Register Contents
MSB
LSB
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Data Bits
A1
PD
LDAC
A0
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