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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD5324ARMZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 20/24闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC 12BIT QUAD VOUT 10MSOP
鐢㈠搧鍩硅〒妯″锛� Data Converter Fundamentals
DAC Architectures
妯欐簴鍖呰锛� 50
瑷疆鏅傞枔锛� 8µs
浣嶆暩(sh霉)锛� 12
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
杞夋彌鍣ㄦ暩(sh霉)鐩細 4
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 105°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 10-TFSOP锛�10-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳鍟嗚ō鍌欏皝瑁濓細 10-MSOP
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 4 闆诲锛屽柈妤碉紱4 闆诲锛岄洐妤�
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Data Sheet
AD5304/AD5314/AD5324
Rev. H | Page 5 of 24
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at TMIN, TMAX
VDD = 2.5 V to 3.6 V
VDD = 3.6 V to 5.5 V
Unit
Test Conditions/Comments
t1
40
33
ns min
SCLK cycle time
t2
16
13
ns min
SCLK high time
t3
16
13
ns min
SCLK low time
t4
16
13
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
80
33
ns min
Minimum SYNC high time
1 Guaranteed by design and characterization, not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90 % of VDD) and timed from a voltage level of (VIL + VIH)/2.
SCLK
DIN
DB15
DB0
t1
t3
t2
t7
t5
t4
t6
t8
SYNC
00
92
9-
0
02
Figure 2. Serial Interface Timing Diagram
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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