參數(shù)資料
型號(hào)： AD5327BRU
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 0K
描述： IC DAC 12BIT QUAD 2.5V 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 4.5mW
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 125k
AD5307/AD5317/AD5327
Rev. C | Page 21 of 28
OPTO-ISOLATED INTERFACE FOR
PROCESS-CONTROL APPLICATIONS
The AD5307/AD5317/AD5327 each have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process-control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5307/AD5317/AD5327 from the controller. This can easily
be achieved by using opto-isolators capable of providing isolation
in excess of 3 kV. The actual data rate achieved can be limited
by the type of optocouplers chosen. The serial loading structure
of the AD5307/AD5317/AD5327 makes them ideally suited for
use in opto-isolated applications. Figure 43 shows an opto-isolated
interface to the AD5307/AD5317/AD5327 where DIN, SCLK,
and SYNC are driven from optocouplers. The power supply to
the part should also be isolated. This is done by using a trans-
former. On the DAC side of the transformer, a 5 V regulator
provides the 5 V supply required for the AD5307/AD5317/
AD5327.
10k
DIN
GND
SCLK
5V
REGULATOR
POWER
10k
AD5307
DCEN
02
06
7-
0
43
SYNC
VOUTB
VOUTC
VOUTD
VREFAB
VREFCD
10F
0.1F
VOUTA
VDD
SCLK
DIN
SYNC
Figure 43. AD5307 in an Opto-Isolated Interface
DECODING MULTIPLE
AD5307/AD5317/AD5327 DEVICES
The SYNC pin on the AD5307/AD5317/AD5327 can be used in
applications to decode a number of DACs. In this application,
all DACs in the system receive the same serial clock and serial
data, but the SYNC to only one of the devices is active at any
given time, allowing access to four channels in this 16-channel
system. The 74HC139 is used as a 2-to-4 line decoder to address
any of the DACs in the system. To prevent timing errors, the
enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 44 shows a
diagram of a typical setup for decoding multiple AD5307
devices in a system.
74HC139
ENABLE
CODED
ADDRESS
1G
1A
1B
DGND
1Y0
1Y1
1Y2
1Y3
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
DIN
SCLK
AD5307
VOUTB
VOUTC
VOUTD
VOUTA
SYNC
VCC
VDD
VOUTB
VOUTC
VOUTD
VOUTA
VOUTB
VOUTC
VOUTD
VOUTA
VOUTB
VOUTC
VOUTD
VOUTA
02067-
044
SYNC
Figure 44. Decoding Multiple AD5307 Devices in a System
AD5307/AD5317/AD5327 AS DIGITALLY
PROGRAMMABLE WINDOW DETECTORS
A digitally programmable upper/lower limit detector using two of
the DACs in the AD5307/AD5317/AD5327 is shown in Figure 45.
The upper and lower limits for the test are loaded to DAC A
and DAC B, which, in turn, set the limits on the CMP04. If the
signal at the VIN input is not within the programmed window,
an LED indicates the fail condition. Similarly, DAC C and DAC D
can be used for window detection on a second VIN signal.
5V
SCLK
DIN
1/2
CMP04
1k
FAIL
1k
PASS
1/6 74HC05
SYNC
10F
0.1F
VREF
VIN
PASS/FAIL
AD5307/
AD5317/
AD5327
SCLK
DIN
GND
VOUTA
VREFAB
VREFCD
VOUTB
SYNC
VDD
020
67-
045
Figure 45. Window Detection
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