參數(shù)資料
型號(hào)： AD5327BRUZ
廠(chǎng)商： Analog Devices Inc
文件頁(yè)數(shù)： 27/28頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT QUAD 2.5V 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 8µs
位數(shù)： 12
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 單電源
功率耗散（最大）： 4.5mW
工作溫度： -40°C ~ 105°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類(lèi)型： 4 電壓，單極；4 電壓，雙極
采樣率（每秒）： 125k
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
AD5307/AD5317/AD5327
Rev. C | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
VDD
VOUTA
VOUTB
VOUTC
VREFAB
VREFCD
SDO
SCLK
DIN
GND
VOUTD
DCEN
AD5307/
AD5317/
AD5327
CLR
LDAC
PD
SYNC
02067-005
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
CLR
Active Low Control Input. Loads all 0s to all input and DAC registers. Therefore, the outputs also go to 0 V.
2
LDAC
Active Low Control Input. Transfers the contents of the input registers to their respective DAC registers. Pulsing this
pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous
update of all DAC outputs. Alternatively, this pin can be tied permanently low.
3
VDD
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
4
VOUTA
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
5
VOUTB
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
6
VOUTC
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
7
VREFAB
Reference Input Pin for DAC A and DAC B. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC A and DAC B. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
8
VREFCD
Reference Input Pin for DAC C and DAC D. It can be configured as a buffered or unbuffered input to each or both of
the DACs, depending on the state of the BUF bits in the serial input words to DAC C and DAC D. It has an input range
of 0.25 V to VDD in unbuffered mode and 1 V to VDD in buffered mode.
9
DCEN
Enables the Daisy-Chaining Option. It should be tied high if the part is being used in a daisy chain, and tied low if it is
being used in standalone mode.
10
PD
Active Low Control Input. It acts like a hardware power-down option. All DACs go into power-down mode when this
pin is tied low. The DAC outputs go into a high impedance state, and the current consumption of the part drops to
300 nA @ 5 V (90 nA @ 3 V).
11
VOUTD
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
12
GND
Ground Reference Point for All Circuitry on the Part.
13
DIN
Serial Data Input. These devices each have a 16-bit shift register. Data is clocked into the register on the falling edge of
the serial clock input. The DIN input buffer is powered down after each write cycle.
14
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be
transferred at rates of up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
15
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it powers
on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the
following 16 clocks. If SYNC is taken high before the 16th falling edge, the rising edge of SYNC acts as an interrupt and
the write sequence is ignored by the device.
16
SDO
Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading back the data in
the shift register for diagnostic purposes. The serial data is transferred on the rising edge of SCLK and is valid on the
falling edge of the clock.
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