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參數(shù)資料
| 型號： | AD5338 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2.5 V to 5.5 V, 250 UA, 2-Wire Interface Dual-Voltage Output, 8-/10-/12-Bit DACs |
| 中文描述： | 2.5 V至5.5 V，250尿酸，2線接口雙電壓輸出，8-/10-/12-Bit數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 654K |
| 代理商： | AD5338 |
AD5337/AD5338/AD5339
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. A | Page 8 of 24
V
DD
V
OUT
A
GND
SDA
SCL
V
OUT
B
REFIN
A0
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
AD5337/
AD5338/
AD5339
0
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1
V
DD
2
V
OUT
A
3
V
OUT
B
4
REFIN
5
GND
6
SDA
Function
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Reference Input Pin for the Two DACs. It has an input range from 0.25 V to V
DD
.
Ground Reference Point for All Circuitry on the Parts.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift
register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up
resistor.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift
register. Clock rates of up to 400 kbps can be accommodated in the 2-wire interface.
Address Input. Sets the least significant bit of the 7-bit slave address.
7
SCL
8
A0
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