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| 型號： | AD5340BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT PAR 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 設(shè)置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 1.25mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 125k |
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AD5330/AD5331/AD5340/AD5341
Rev. A | Page 18 of 28
PARALLEL INTERFACE
The AD5330, AD5331, and AD5340 load their data as a single
8-, 10-, or 12-bit word, while the AD5341 loads data as a low
byte of eight bits and a high byte containing four bits.
DOUBLE-BUFFERED INTERFACE
The AD5330/AD5331/AD5340/AD5341 DACs all have double-
buffered interfaces consisting of an input register and a DAC
register. DAC data, BUF, and GAIN inputs are written to the
input register under the control of chip select (CS) and write (WR).
Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain and buffer control signals
are also double-buffered and are only updated when LDAC is
taken low.
Double-buffering is also useful where the DAC data is loaded
in two bytes, as in the AD5341, because it allows the whole
data word to be assembled in parallel before updating the DAC
register. This prevents spurious outputs that can occur if the DAC
register is updated with only the high byte or the low byte.
These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC register is filled with the
contents of the input register. In the case of the AD5330/
AD5331/AD5340/AD5341, the parts only update the DAC
register if the input register has been changed since the last time
the DAC register was updated. This removes unnecessary crosstalk.
CLEAR INPUT (CLR)
CLR is an active low, asynchronous clear that resets the input
and DAC registers.
CHIP SELECT INPUT (CS)
CS is an active low input that selects the device.
WRITE INPUT (WR)
WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising
edge of WR.
LOAD DAC INPUT (LDAC)
LDAC transfers data from the input register to the DAC register
(and therefore updates the outputs). Use of the LDAC function
enables double-buffering of the DAC data, GAIN, and BUF.
There are two LDAC modes: synchronous mode and
asynchronous mode.
In synchronous mode, the DAC register is updated after new
data is read in on the rising edge of the WR input. LDAC can
be tied permanently low or pulsed, as shown in
In asynchronous mode, the outputs are not updated at the same
time that the input register is written to. When LDAC goes low,
the DAC register is updated with the contents of the input
register.
HIGH BYTE ENABLE INPUT (HBEN)
High byte enable is a control input on the AD5341 only. It
determines if data is written to the high byte input register
or the low byte input register.
The low data byte of the AD5341 consists of Data Bits [0:7]
at the data inputs DB0 to DB7, whereas the high byte consists
of Data Bits [8:11] at the data inputs DB0 to DB3, as shown in
they can be used for data to set up the reference input as buffered/
unbuffered, and buffer amplifier gain (see Figure 42).
DB8
DB9
X
HIGH BYTE
LOW BYTE
X = UNUSED BIT
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
XX
DB10
DB11
06
85
2-
03
9
Figure 38. Data Format for AD5341
POWER-ON RESET
The AD5330/AD5331/AD5340/AD5341 are provided with a
power-on reset function, so that they power up in a defined
state. The power-on state is
Normal operation
Reference input unbuffered
0 V to VREF output range
Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
as such until a valid write sequence is made to the device. This
is particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
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