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參數(shù)資料
| 型號： | AD5344BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD VOUT 28-TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 50 |
| 設置時間： | 8µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 4.5mW |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 28-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 125k |
| 產(chǎn)品目錄頁面： | 782 (CN2011-ZH PDF) |
REV. 0
AD5334/AD5335/AD5336/AD5344
–7–
AD5336 FUNCTIONAL BLOCK DIAGRAM
VOUTA
BUFFER
GND
AD5336
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
BUFFER
POWER-ON
RESET
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
PD
DAC
REGISTER
INPUT
REGISTER
VREFC
INTER-
FACE
LOGIC
VDD
VREFB
GAIN
DB9
DB0
CS
WR
A0
A1
CLR
LDAC
.
VREFA
VREFD
RESET
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
10-BIT
DAC
AD5336 PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
1VREFD
Unbuffered Reference Input for DAC D.
2VREFC
Unbuffered Reference Input for DAC C.
3VREFB
Unbuffered Reference Input for DAC B.
4VREFA
Unbuffered Reference Input for DAC A.
5VOUTA
Output of DAC A. Buffered output with rail-to-rail operation.
6VOUTB
Output of DAC B. Buffered output with rail-to-rail operation.
7VOUTC
Output of DAC C. Buffered output with rail-to-rail operation.
8VOUTD
Output of DAC D. Buffered output with rail-to-rail operation.
9
GND
Ground Reference Point for All Circuitry on the Part.
10
CS
Active Low Chip Select Input. This is used in conjunction with
WR to write data to the parallel interface.
11
WR
Active Low Write Input. This is used in conjunction with
CS to write data to the parallel interface.
12
A0
LSB Address Pin for Selecting which DAC Is to Be Written to.
13
A1
MSB Address Pin for Selecting which DAC is to Be Written to.
14
LDAC
Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
15
PD
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
16
VDD
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10
F capacitor in parallel with a 0.1 F capacitor to GND.
17–26
DB0–DB9
10 Parallel Data Inputs. DB9 is the MSB of these 10 bits.
27
GAIN
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF.
28
CLR
Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
AD5336 PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD5336
LDAC
A1
A0
WR
CS
GND
VOUTD
VREFC
VREFB
VREFA
VOUTC
VOUTB
VOUTA
VREFD
PD
VDD
DB0
DB1
DB2
DB3
DB4
CLR
GAIN
DB9
DB8
DB5
DB6
DB7
10-BIT
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| AD5344BRUZ-REEL | 功能描述:IC DAC 12BIT QUAD VOUT 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:2,400 系列:- 設置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應商設備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD5344BRUZ-REEL7 | 功能描述:IC DAC 12BIT QUAD VOUT 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:47 系列:- 設置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5346 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.5 V to 5.5 V, Parallel Interface 2.5 V to 5.5 V, Parallel Interface |
| AD5346BCP | 制造商:Analog Devices 功能描述:DAC 8-CH Resistor-String 8-bit 40-Pin LFCSP EP 制造商:Analog Devices 功能描述:IC 8BIT DAC SERIAL I/F OCTAL 5346 |
| AD5346BCP-REEL | 制造商:Analog Devices 功能描述:DAC 8-CH Resistor-String 8-bit 40-Pin LFCSP EP T/R |
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