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參數(shù)資料
| 型號(hào)： | AD53519 |
| 英文描述： | AD53519: Dual Ultrafast Voltage Comparator Preliminary Data Sheet (Rev.PrJ. 8/02) |
| 中文描述： | AD53519：雙超高速電壓比較器的初步數(shù)據(jù)（Rev.PrJ。8月2日） |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 592K |
| 代理商： | AD53519 |
PRELIMINARY TECHNICAL DATA
AD53519
TIMING INFORMATION
REV. Pr J July 22, 2002
- 6 -
The timing diagram is presented to illustrate the AD53519 compare and latch features.
SYSTEM TIMING DIAGRAM
LATCH ENABLE
/LATCH ENABLE
50%
VREF± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
Q OUTPUT
/Q OUTPUT
tS
VIN
VOD
tPL
tPLOH
tPDL
tH
50%
tPLOL
tPDH
tR
tF
Figure 3
Terms used in timing diagrams:
t
PDH
INPUT TO OUTPUT HIGH
DELAY
INPUT TO OUTPUT LOW
DELAY
LATCH ENABLE TO
OUTPUT HIGH DELAY
LATCH ENABLE TO
OUTPUT LOW DELAY
MINIMUM HOLD TIME
The propagation delay measured from the time the input signal crosses the reference (
±
the input offset voltage) to the 50% point of an output LOW to HIGH transition
The propagation delay measured from the time the input signal crosses the reference (
±
the input offset voltage) to the 50% point of an output HIGH to LOW transition
The propagation delay measure from the 50% point of the Latch Enable signal LOW to
HIGH transition to the 50% point of an output LOW to HIGH transition
The propagation delay measured from the 50% point of the Latch Enable signal LOW
to HIGH transition to the 50% point of an output HIGH to LOW transition
The minimum time after the negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be acquired and held at the outputs
The minimum time that the Latch Enable signal must be HIGH in order to acquire and
input signal change
The minimum time before the negative transition of the Latch Enable signal that an
input signal change must be present in order to be acquired and held at the outputs
The amount of time required to transition from a LOW to HIGH output as measured at
the 20 and 80% points
The amount of time required to transition from a HIGH to LOW output as measured at
the 20 and 80% points
The difference between the differential input and reference input voltages
t
PDL
t
PLOH
t
PLOL
t
H
t
PL
MINIMUM LATCH
ENABLE PULSE WIDTH
MINIMUM SETUP TIME
t
S
t
R
OUTPUT RISE TIME
t
F
OUTPUT FALL TIME
V
OD
VOLTAGE OVERDRIVE
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