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參數(shù)資料
| 型號(hào)： | AD5361BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 16CH SERIAL 56LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 16 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 245mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 16 電壓，單極；16 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5361EBZ-ND - BOARD EVAL FOR AD5361 |
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AD5360/AD5361
Rev. A | Page 18 of 28
4.
Choose the new required VOUTMAX and VOUTMIN, keeping
the VOUT limits centered on the nominal values. Note that
VDD and VSS must provide sufficient headroom.
5.
Calculate the value of VREF as follows:
VREF = (VOUTMAX VOUTMIN)/4
Reference Selection Example
Nominal output range = 20 V (10 V to +10 V)
Offset error = ±100 mV
Gain error = ±3%
SIGGND = AGND = 0 V
Gain error = ±3%
Maximum positive gain error = +3%
Output range including gain error = 20 + 0.03 (20) =
20.6 V
Offset error = ±100 mV
Maximum offset error span = 2 (100 mV) = 0.2 V
Output range including gain error and offset error =
20.6 V + 0.2 V = 20.8 V
VREF calculation
Actual output range = 20.6 V, that is, 10.3 V to +10.3 V
(centered);
VREF = (10.3 V + 10.3 V)/4 = 5.15 V
If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:
Use a resistor divider to divide down a convenient, higher
reference level to the required level.
Select a convenient reference level above VREF and modify
the gain and offset registers to digitally downsize the
reference. In this way, the user can use almost any conven-
ient reference level but may reduce the performance by
overcompaction of the transfer function.
Use a combination of these two approaches.
CALIBRATION
The user can perform a system calibration on the AD5360 and
AD5361 to reduce gain and offset errors to below 1 LSB. This is
achieved by calculating new values for the M and C registers and
reprogramming them.
Reducing Zero-Scale and Full-Scale Error
Zero-scale error can be reduced as follows:
1.
Set the output to the lowest possible value.
2.
Measure the actual output voltage and compare it with the
required value. This gives the zero-scale error.
3.
Calculate the number of LSBs equivalent to the error and
add this from the default value of the C register. Note that
only negative zero-scale error can be reduced.
Full-scale error can be reduced as follows:
1.
Measure the zero-scale error.
2.
Set the output to the highest possible value.
3.
Measure the actual output voltage and compare it with the
required value. Add this error to the zero-scale error. This
is the span error, which includes full-scale error.
4.
Calculate the number of LSBs equivalent to the span error
and subtract it from the default value of the M register.
Note that only positive full-scale error can be reduced.
The M and C registers should not be programmed until both
zero-scale errors and full-scale errors have been calculated.
AD5360 Calibration Example
This example assumes that a 10 V to +10 V output is required.
The DAC output is set to 10 V but is measured at 10.03 V.
This gives a zero-scale error of 30 mV.
1 LSB = 20 V/65,536 = 305.176 μV
30 mV = 98 LSBs
The full-scale error can now be removed. The output is set
to +10 V, and a value of +10.02 V is measured. The full-scale
error is +20 mV. The span error is +20 mV (30 mV) =
+50 mV.
+50 mV = 164 LSBs
The errors can now be removed.
1.
98 LSBs should be added to the default C register value;
(32,768 + 98) = 32,866.
2.
32,866 should be programmed to the C register.
3.
164 LSBs should be subtracted from the default M register
value; (65,535 164) = 65,371.
4.
65,371 should be programmed to the M register.
Additional Calibration
The techniques described in the previous section are usually
enough to reduce the zero-scale errors and full-scale errors in
most applications. However, there are limitations whereby the
errors may not be sufficiently removed. For example, the offset
(C) register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.
These limitations can be overcome by increasing the refer-
ence value. With a 2.5 V reference, a 10 V span is achieved.
The ideal voltage range, for the AD5360 or AD5361, is
5 V to +5 V. Using a 2.6 V reference increases the range
to 5.2 V to +5.2 V. Clearly, in this case, the offset and gain
errors are insignificant and the M and C registers can be
used to raise the negative voltage to 5 V and then reduce
the maximum voltage down to +5 V to give the most
accurate values possible.
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| AD5361BCPZ-REEL7 | 功能描述:IC DAC 14BIT 16CH SERIAL 56LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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