參數(shù)資料
型號(hào): AD5370BCPZ
廠商: Analog Devices Inc
文件頁數(shù): 14/29頁
文件大小: 0K
描述: IC DAC 16BIT 40CH SERIAL 64LFCSP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: 40 Channels of Programmable Output Span Using AD5371 (CN0149)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 雙 ±
功率耗散(最大): 610mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 托盤
輸出數(shù)目和類型: 40 電壓,單極;40 電壓,雙極
AD5370
Rev. 0 | Page 20 of 28
TOGGLE MODE
The AD5370 has two X2 registers per channel, X2A and X2B,
that can be used to switch the DAC output between two levels
with ease. This approach greatly reduces the overhead required
by a microprocessor that would otherwise have to write to each
channel individually. When the user writes to the X1A, X2A, M,
or C register, the calculation engine takes a certain amount of
time to calculate the appropriate X2A or X2B value. If the
application only requires that the DAC output switch between
two levels, as is the case with a data generator, any method that
reduces the amount of calculation time necessary is advantageous.
For the data generator example, the user need only set the high
and low levels for each channel once by writing to the X1A and
X1B registers. The values of X2A and X2B are calculated and
stored in their respective registers. The calculation delay
therefore happens only during the setup phase, that is, when
programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the
relevant A/B select register to set the MUX2 register bit. Further-
more, because there are eight MUX2 control bits per register, it
is possible to update eight channels with a single write. Table 15
shows the bits that correspond to each DAC output.
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