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參數(shù)資料
| 型號： | AD5371BSTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 40CH SER 80-LQFP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 40 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（12x12） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 40 電壓，單極；40 電壓，雙極 |
| 采樣率（每秒）： | * |
| 配用： | EVAL-AD5371EBZ-ND - BOARD EVAL FOR AD5371 |
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AD5371
Rev. B | Page 20 of 28
RESET FUNCTION
The reset function is initiated by the RESET pin. On the rising
edge of RESET, the AD5371 state machine initiates a reset
sequence to reset the X, M, and C registers to their default values.
This sequence typically takes 300 μs, and the user should not
write to the part during this time. On power-up, it is recom-
mended that the user bring RESET high as soon as possible to
properly initialize the registers.
When the reset sequence is complete (and provided that CLR is
high), the DAC output is at a potential specified by the default
register settings, which is equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and LDAC is taken low. The AD5371 can be returned
to the default state by pulsing RESET low for at least 30 ns. Note
that, because the reset function is triggered by the rising edge,
bringing RESET low has no effect on the operation of the AD5371.
CLEAR FUNCTION
CLR is an active low input that should be high for normal oper-
ation. The CLR pin has an internal 500 kΩ pull-down resistor.
When CLR is low, the input to each of the DAC output buffer
stages, VOUT0 to VOUT39, is switched to the externally set
potential on the relevant SIGGNDx pin. While CLR is low, all
LDAC pulses are ignored. When CLR is taken high again, the
DAC outputs return to their previous values. The contents of
the input registers and the DAC registers are not affected by
taking CLR low. To prevent glitches from appearing on the
outputs, bring CLR low before writing to the offset DAC to
adjust the output span.
BUSY AND LDAC FUNCTIONS
The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the BUSY output goes low. While
BUSY is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
details), but no DAC output updates can take place.
The BUSY pin is bidirectional and has a 50 kΩ internal pull-up
resistor. When multiple AD5371 devices are used in one system,
the BUSY pins can be tied together. This is useful when it is
required that no DAC in any device be updated until all other
DACs are ready to be updated. When each device has finished
updating the X2 (A or B) register, it releases the BUSY pin. If
another device has not finished updating its X2 register, it holds
BUSY low, thus delaying the effect of LDAC going low.
The DAC outputs are updated by taking the LDAC input low. If
LDAC goes low while BUSY is active, the LDAC event is stored
and the DAC outputs are updated immediately after BUSY goes
high. A user can also hold the LDAC input permanently low.
In this case, the DAC outputs are updated immediately after
BUSY goes high. Whenever the A/B select registers are written
to, BUSY also goes low for approximately 500 ns.
The AD5371 has flexible addressing that allows writing of data
to a single channel, all channels in a group, the same channel in
Group 0 to Group 4, the same channel in Group 1 to Group 4, or
all channels in the device. This means that 1, 4, 5, 8, or 40 DAC
register values may need to be calculated and updated. Because
there is only one multiplier shared among 40 channels, this task
must be done sequentially so that the length of the BUSY pulse
varies according to the number of channels being updated.
Table 9. BUSY Pulse Widths
Action
BUSY Pulse Width1
Loading X1A, X1B, C, or M to 1 channel2
1.5 μs maximum
Loading X1A, X1B, C, or M to 5 channels
3.9 μs maximum
Loading X1A, X1B, C, or M to 8 channels
5.7 μs maximum
Loading X1A, X1B, C, or M to 40 channels
24.9 μs maximum
1
BUSY pulse width = ((number of channels + 1) × 600 ns) + 300 ns.
2 A single channel update is typically 1 μs.
The AD5371 contains an extra feature whereby a DAC register
is not updated unless its X2A or X2B register has been written
to since the last time LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the contents
of the X2A or X2B register, depending on the setting of the A/B
select registers. However, the AD5371 updates the DAC register
only if the X2A or X2B data has changed, thereby removing
unnecessary digital crosstalk.
POWER-DOWN MODE
The AD5371 can be powered down by setting Bit 0 in the
control register to 1. This turns off the DACs, thus reducing the
current consumption. The DAC outputs are connected to their
respective SIGGNDx potentials. The power-down mode does
not change the contents of the registers, and the DACs return to
their previous voltage when the power-down bit is cleared to 0.
THERMAL SHUTDOWN FUNCTION
The AD5371 can be programmed to shut down the DACs if
the temperature on the die exceeds 130°C. Setting Bit 1 in the
control register to 1 enables this function (see Table 17). If the
die temperature exceeds 130°C, the AD5371 enters a thermal
shutdown mode that is equivalent to setting the power-down bit
in the control register to 1. To indicate that the AD5371 has
entered thermal shutdown mode, Bit 4 of the control register is
set to 1. The AD5371 remains in thermal shutdown mode, even
if the die temperature falls, until Bit 1 in the control register is
cleared to 0.
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| AD5372BCPZ-RL7 | 功能描述:16 Bit Digital to Analog Converter 32 56-LFCSP-VQ (8x8) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):上次購買時間 位數(shù):16 數(shù)模轉(zhuǎn)換器數(shù):32 建立時間:30μs 輸出類型:Voltage - Buffered 差分輸出:無 數(shù)據(jù)接口:SPI，DSP 參考類型:外部 電壓 - 電源，模擬:9 V ~ 16.5 V，-4.5 V ~ 16.5 V 電壓 - 電源，數(shù)字:2.5 V ~ 5.5 V INL/DNL（LSB）:±4（最大），±1（最大） 架構:電阻串 DAC 工作溫度:-40°C ~ 85°C 封裝/外殼:56-VFQFN 裸露焊盤，CSP 供應商器件封裝:56-LFCSP-VQ（8x8） 標準包裝:1 |
| AD5372BSTZ | 功能描述:IC DAC 16BIT 32CH SER 64-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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