VDD SIGGND2 VOUT20 VOUT21 VOUT23 VREF0 VOUT0 VOUT1 VOUT3 VOUT4 VOUT6" />
參數(shù)資料
型號(hào): AD5371BSTZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 4/29頁(yè)
文件大?。?/td> 0K
描述: IC DAC 14BIT 40CH SER 80-LQFP
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 20µs
位數(shù): 14
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 40
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(12x12)
包裝: 托盤
輸出數(shù)目和類型: 40 電壓,單極;40 電壓,雙極
采樣率(每秒): *
AD5371
Rev. B | Page 11 of 28
DGND
VDD
SIGGND2
VOUT20
VOUT21
VOUT23
VREF0
VOUT0
VOUT1
VOUT3
VOUT4
VOUT6
DGND
VOUT18
VDD
VOUT19
VOUT22
VREF2
NC
VOUT2
SIGGND0
VOUT5
VOUT7
DVCC
VOUT16
VOUT17
DVCC
SYNC
VOUT14
VOUT15
VDD
AGND
SYNC
SCLK
VOUT12
VOUT13
VDD
AGND
SCLK
SDI
VOUT11
SIGGND1
VDD
AGND
SDI
SPI/
LVDS
VOUT9
VOUT10
VDD
AGND
NC
TESTO
VOUT39
VOUT8
VDD
AGND
SDO
LDAC
VREF1
VOUT38
VSS
AGND
RESET
CLR
VOUT37
SIGGND4
BUSY
NC
VOUT36
VSS
VOUT34
VOUT32
VOUT30
VOUT28
NC
VOUT24
VOUT25
AGND
TESTI
AGND
12
11
10
9
87
654
32
1
VSS
VOUT35
VOUT33
VOUT31
VOUT29
NC
SIGGND3
VOUT27
VOUT26
AGND
A
M
L
K
J
H
G
F
E
D
C
B
05
81
4-
0
25
Figure 8. 100-Ball Grid Array Pin Configuration—Bottom View
Table 7. Pin Function Descriptions
Pin No.
Ball No.
Mnemonic
Description
1
A4
LDAC
Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions section for more
information.
2
A3
CLR
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for
more information.
3
B4
RESET
Digital Reset Input.
4
B3
BUSY
Digital Input/Open-Drain Output
. BUSY is open drain when an output. See the BUSY and LDAC
Functions section for more information.
5
B2
TESTI
Test Input Pin. Connect this pin to DGND.
73
A5
TESTO
Test Output Pin. This pin remains unconnected.
54 to 57,
60 to 63,
27 to 30,
32 to 34,
36 to 40,
46 to 49,
78 to 80,
6, 8 to 15,
17, 18,
25, 26
F12, E12, E11,
D12, C12, C11,
B12, B11, L5,
M6, L6, M7,
M8, L8, M9, L9,
M10, L10, M11,
K11, K12, J12,
J11, H12, E2,
D2, D1, E1, G2,
H1, H2, J1, J2,
K1, K2, L1, M2,
M3, L4, M5
VOUT0 to
VOUT39
DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output
is capable of driving an output load of 10 kΩ to ground. Typical output impedance of these
amplifiers is 0.5 Ω.
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