參數(shù)資料
型號(hào)： AD5372BSTZ-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 8/29頁
文件大小： 0K
描述： IC DAC 16BIT 32CH SER 64-LQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,500
設(shè)置時(shí)間： 20µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 32
電壓電源： 雙 ±
功率耗散（最大）： 520mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 32 電壓，單極；32 電壓，雙極
采樣率（每秒）： *
配用： EVAL-AD5372EBZ-ND - BOARD EVAL FOR AD5372
AD5372/AD5373
Rev. C | Page 15 of 28
THEORY OF OPERATION
DAC ARCHITECTURE
The AD5372/AD5373 contain 32 DAC channels and 32 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit (AD5372) or 14-bit (AD5373)
resistor-string DAC followed by an output buffer amplifier.
The resistor-string section is simply a string of resistors (of
equal value) from VREF0 or VREF1 to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit
(AD5372) or 14-bit (AD5373) binary digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off before being fed into the output amplifier.
The output amplifier multiplies the DAC output voltage by 4.
The nominal output span is 12 V with a 3 V reference and 20 V
with a 5 V reference.
CHANNEL GROUPS
The 32 DAC channels of the AD5372/AD5373 are arranged into
four groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 3 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.
Table 7. AD5372/AD5373 Registers
Register Name
Word Length
in Bits
Description
X1A (Group) (Channel)
16 (14)
Input Data Register A, one for each DAC channel.
X1B (Group) (Channel)
16 (14)
Input Data Register B, one for each DAC channel.
M (Group) (Channel)
16 (14)
Gain trim registers, one for each DAC channel.
C (Group) (Channel)
16 (14)
Offset trim registers, one for each DAC channel.
X2A (Group) (Channel)
16 (14)
Output Data Register A, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
X2B (Group) (Channel)
16 (14)
Output Data Register B, one for each DAC channel. These registers store the final, calibrated
DAC data after gain and offset trimming. They are not readable or directly writable.
DAC (Group) (Channel)
Data registers from which the DACs take their final input data. The DAC registers are updated
from the X2A or X2B registers. They are not readable or directly writable.
OFS0
14
Offset DAC 0 data register: sets offset for Group 0.
OFS1
14
Offset DAC 1 data register: sets offset for Group 1 to Group 3.
Control
3
Bit 2 = A/B.
0 = global selection of X1A input data registers.
1 = global selection of X1B input data registers.
Bit 1 = enable thermal shutdown.
0 = disable thermal shutdown.
1 = enable thermal shutdown.
Bit 0 = software power-down.
0 = software power-up.
1 = software power-down.
A/B Select 0
8
Each bit in this register determines whether a DAC in Group 0 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 1
8
Each bit in this register determines whether a DAC in Group 1 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 2
8
Each bit in this register determines whether a DAC in Group 2 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
A/B Select 3
8
Each bit in this register determines whether a DAC in Group 3 takes its data from Register X2A
or Register X2B (0 = X2A, 1 = X2B).
Table 8. AD5372/AD5373 Input Register Default Values
Register Name
AD5372 Default Value
AD5373 Default Value
X1A, X1B
0x5554
0x1555
M
0xFFFF
0x3FFF
C
0x8000
0x2000
OFS0, OFS1
0x1555
Control
0x00
A/B Select 0 to A/B Select 3
0x00
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