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參數(shù)資料
| 型號： | AD537SD |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 683K |
| 描述： | IC V/F CONV 14-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 電壓至頻率 |
| 頻率 - 最大： | 100kHz |
| 全量程： | ±30ppm/°C |
| 線性： | ±0.05% |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 14-CDIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 14-CDIP |
| 包裝： | 管件 |
AD537
REV. C
4
The V
IN
, +V
IN
and I
IN
pins should not be driven more than
300mV below V
S
. This would cause internal junctions to con-
duct, possibly damaging the IC. The AD537 can be protected
from below V
S
inputs by a Schottky diode, CR1 (HP5082-
2811) as shown in Figure 3. It is also desirable not to drive
+V
IN
, V
IN
and I
IN
above +V
S
. In operation, the converter will
become very nonlinear for inputs above (+V
S
3.5V). Control
currents above 2mA will also cause nonlinearity.
The 80 dB dynamic range of the AD537 guarantees operation
from a control current of 1mA (nominal FS) down to 100nA
(equivalent to 1mV to 10V FS). Below 100nA improper op-
eration of the oscillator may result, causing a false indication of
input amplitude. In many cases this might be due to short-lived
noise spikes which become added to the input. For example,
when scaled to accept a FS input of 1 V, the 80dB level is
only 100礦, so when the mean input is only 60dB below FS
(1mV), noise spikes of 0.9mV are sufficient to cause momen-
tary malfunction.
This effect can be minimized by using a simple low-pass filter
ahead of the converter and a guard ring around the I
IN
or V
IN
pins. For a FS of 10kHz a single-pole filter with a time-constant
of 100ms (Figure 2) will be suitable, but the optimum configu-
ration will depend on the application and type of signal process-
ing. Noise spikes are only likely to be a cause of error when the
input current remains near its minimum value for long periods
of time; above 100nA (1mV) full integration of additive input
noise occurs.
The AD537 is somewhat susceptible to interference from other
signals. The most sensitive nodes (besides the inputs) are the
capacitor terminals and the SYNC pin. The timing capacitor
should be located as close as possible to the AD537 to minimize
signal pickup in the leads. In some cases, guard rings or shield-
ing may be required. The SYNC pin should be decoupled
through a 0.005礔 (or larger) capacitor to Pin 13 (+V
S
). This
minimizes the possibility that the AD537 will attempt to syn-
chronize to a spurious signal. This precaution is unnecessary on
the metal can package since the SYNC function is not brought
out to a package pin and is thus not susceptible to pickup.
DECOUPLING
It is good engineering practice to use bypass capacitors on the
supply-voltage pins and to insert small-valued resistors (10& to
100&) in the supply lines to provide a measure of decoupling
between the various circuits in a system. Ceramic capacitors of
0.1礔 to 1.0礔 should be applied between the supply-voltage
pins and analog signal ground for proper bypassing on the
AD537.
A decoupling capacitor may also be useful from +V
S
to SYNC
in those applications where very low cycle-to-cycle period varia-
tion (jitter) is demanded. By placing a capacitor across +V
S
and
SYNC this noise is reduced. On the 10kHz FS range, a 6.8礔
capacitor reduces the jitter to one in 20,000 which adequate for
most applications. A tantalum capacitor should be used to avoid
errors due to dc leakage.
In some cases the signal may be in the form of a negative cur-
rent source. This can be handled in a similar way to a negative
input voltage. However, the scaling resistor is no longer re-
quired, eliminating the capability of trimming full scale in this
fashion. Since it will usually be impractical to vary the capaci-
tance, an alternative calibration scheme is needed. This is
shown in Figure 3. A resistor-potentiometer connected from
the V
R
output to V
S
will alter the internal operating conditions
in a predictable way, providing the necessary adjustment range.
With the values shown, a range of ?% is available; a larger
range can be attained by reducing R1. This technique does not
degrade the temperature-coefficient of the converter, and the
linearity will be as for negative input voltages. The minimum
supply voltage may be used.
Unless it is required to set the input node at exactly ground
potential, no offset adjustment is needed. The capacitor C is se-
lected to be 5% below the nominal value; with R2 in its
midposition the output frequency is given by:
f =
I
10.5?SPAN class="pst AD537SD_2632449_4">C
where f is in kHz, I is in mA and C is in 礔. For example, for a
FS frequency of 10kHz at a FS input of 1mA, C = 9500pF.
Calibration is effected by applying the full-scale input and ad-
justing R2 for the correct reading.
This alternative adjustment scheme may also be used when it is
desired to present an exact input resistance in the negative volt-
age mode. The scaling relationship is then
f =
V
R
EXACT
?/DIV>
1
10.5C
The calibration procedure is then similar to that used for posi-
tive input voltages, except that the scale adjustment is by means
of R2.
1
2
14
13
5
6
7
10
9
8
3
4
12
11
AD537
R1
27k
R2
200k
C
+V
S
I
IN
10C
f =
OUTPUT
V
LOGIC
CAP
V
S
V
OS
V
OS
LOGIC GND
I
V
ADJ.
SCALE
DEC/SYN
V
TEMP
V
REF
BUF
DRIVER
CURR-
TO-FREQ
CONV
PRECISION
VOLTAGE
REFERENCE
V
T
V
R
I
IN
Figure 3. Scale Adjustment for Current Inputs
INPUT PROTECTION
The AD537 was designed to be used with a minimum of addi-
tional hardware. However, the successful application of a preci-
sion IC involves a good understanding of possible pitfalls and
the use of suitable precautions.
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