參數(shù)資料
型號： AD5415YRU
廠商： Analog Devices Inc
文件頁數(shù)： 14/29頁
文件大?。?/td> 0K
描述： IC DAC DUAL 12BIT MULT 24-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 62
設(shè)置時間： 120ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
AD5415
Data Sheet
Rev. E | Page 20 of 28
SERIAL INTERFACE
The AD5415 has an easy to use 3-wire interface that is
compatible with SPI, QSPI, MICROWIRE, and most DSP
interface standards. Data is written to the device in 16-bit
words. Each 16-bit word consists of four control bits and
12 data bits, as shown in Figure 40.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
only powers up fully when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bits C3 to C0
Control Bits C3 to C0 allow control of various functions of the
DAC, as shown in Table 11. Default settings of the DAC at
power on are as follows. Data is clocked into the shift register
on falling clock edges, and daisy-chain mode is enabled. The
device powers on with a zero-scale load to the DAC register and
IOUT lines. The DAC control bits allow the user to adjust certain
features at power on. For example, daisy-chaining can be
disabled when not in use, an active clock edge can be changed
to a rising edge, and DAC output can be cleared to either zero
scale or midscale. The user can also initiate a readback of the
DAC register contents for verification purposes.
Control Register (Control Bits = 1101)
While maintaining software compatibility with single-channel
current output DACs (AD5426/AD5433/AD5443), this DAC
also features additional interface functionality. Simply set the
control bits to 1101 to enter control register mode. Figure 41
shows the contents of the control register, the functions of
which are described in the following sections.
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-
drain driver. The strength of the SDO driver affects the timing
of t12 and, when stronger, allows a faster clock cycle to be used.
Note that when the SDO output is disabled the daisy-chain
mode is also disabled.
Table 10. SDO Control Bits
SDO2
SDO1
Function
0
Full SDO driver
0
1
Weak SDO driver
1
0
SDO configured as open drain
1
Disable SDO output
Daisy-Chain Control (DSY)
DSY enables or disables daisy-chain mode. A 1 enables daisy-
chain mode; a 0 disables it. When disabled, a readback request
is accepted, SDO is automatically enabled, the DAC register
contents of the relevant DAC are clocked out on SDO, and,
when complete, SDO is disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR pin is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
clears the DAC outputs to midscale; a 0 clears them to zero scale.
Active Clock Edge (SCLK)
The default active clock edge is the falling edge. Write a 1 to this
bit to clock data in on the rising edge; write a 0 to clock it in on
the falling edge.
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB0 (LSB)
DB15 (MSB)
04461-039
Figure 40. 12-Bit Input Shift Register Contents
CONTROL BITS
1
0
1
SDO1
SDO2
DSY
HCLR
SCLK
X
DB0 (LSB)
DB15 (MSB)
04461-040
Figure 41. Control Register Loading Sequence
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