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| 型號： | AD5420ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SRL 40LFCSP |
| 設(shè)計資源： | Simplified 16-Bit, 4 mA-to-20 mA Output Solution Using AD5420 (CN0098) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時間： | 10µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 950mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類型： | 1 電流，單極 |
| 采樣率（每秒）： | * |
| 其它名稱： | AD5420ACPZ-REEL7DKR |
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Data Sheet
AD5410/AD5420
Rev. F | Page 25 of 32
IOUT FILTERING CAPACITORS
Capacitors can be placed between CAP1 and AVDD, and CAP2
AD5410/
AD5420
CAP1
CAP2
07027-
037
AVDD
GND
C1
C2
IOUT
Figure 44. IOUT Filtering Capacitors
The capacitors form a filter on the current output circuitry, as
shown in Figure 45, reducing the bandwidth and the slew rate
of the output current. Figure 46 shows the effect the capacitors
have on the slew rate of the output current. To achieve significant
reductions in the rate of change, very large capacitor values are
required, which may not be suitable in some applications. In
this case, the digital slew rate control feature should be used.
The capacitors can be used in conjunction with the digital slew
rate control feature as a means of smoothing out the steps caused
by the digital code increments, as shown in Figure 47.
BOOST
CAP1
4k
40
DAC
12.5k
RSET
CAP2
IOUT
C1
C2
AVDD
07027-
038
Figure 45. IOUT Filter Circuitry
0
5
10
15
20
25
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
O
UT
P
UT
CURRE
NT
(
mA)
TIME (ms)
NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2
07027-
142
TA = 25°C
AVDD = 24V
RLOAD = 300
Figure 46. Slew Controlled 4 mA to 20 mA Output Current Step Using
External Capacitors on the CAP1 and CAP2 Pins
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
–1
0
1
2
3
4
5
6
7
8
O
UT
P
UT
CURRE
NT
(
mA)
TIME (ms)
TA = 25°C
AVDD = 24V
RLOAD = 300
NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2
07027-
043
Figure 47. Smoothing Out the Steps Caused by the Digital Slew Rate Control
Feature
FEEDBACK/MONITORING OF OUTPUT CURRENT
For feedback or monitoring of the output current value, a sense
resistor can be placed in series with the IOUT output pin and the
voltage drop across it measured. As well as being an additional
component, the resistor increases the compliance voltage
required. An alternative method is to use a resistor that is
already in place. R3 is such a resistor and is internal to the
voltage between the R3SENSE and BOOST pins, the value of the
output current can be calculated as follows:
BIAS
R
OUT
I
R
V
I
=
3
(2)
where:
VR3 is the voltage drop across R3 measured between the R3SENSE
and BOOST pins.
IBIAS is a constant bias current flowing through R3 with a typical
value of 444 A.
R3 is the resistance value of resistor R3 with a typical value of 40 Ω.
AVDD
RMETAL
R3
40
444A
IBIAS
R3SENSE
IOUT
BOOST
07027-
050
Figure 48. Structure of Current Output Circuit
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