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| 型號： | AD5422BCPZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 32 us SETTLING TIME, 16-BIT DAC, QCC40 |
| 封裝： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件頁數(shù)： | 19/40頁 |
| 文件大?。?/td> | 1323K |
| 代理商： | AD5422BCPZ-REEL |
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AD5412/AD5422
Rev. C | Page 26 of 40
THEORY OF OPERATION
The AD5412/AD5422 are precision digital-to-current loop and
voltage output converters designed to meet the requirements of
industrial process control applications. They provide a high
precision, fully integrated, low cost single-chip solution for
generating current loop and unipolar/bipolar voltage outputs.
Current ranges are 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA
to 20 mA; the voltage ranges available are 0 V to 5 V, ±5 V, 0 V
to 10 V, and ±10 V; a 10% overrange is available on all voltage
output ranges. The current and voltage outputs are available on
separate pins, and only one is active at any time. The desired
output configuration is user selectable via the control register.
ARCHITECTURE
The DAC core architecture of the AD5412/AD5422 consists
of two matched DAC sections. A simplified circuit diagram is
shown in Figure 63. The four MSBs of the 12-/16-bit data-word
are decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
word drive the S0 to S7/S11 switches of an 8-/12-bit voltage
mode R-2R ladder network.
8-12 BIT R-2R LADDER
FOUR MSBs DECODED INTO
15 EQUAL SEGMENTS
2R
S0
S1
S7/S11
E1
E2
E15
VOUT
2R
06
99
6-
05
7
Figure 63. DAC Ladder Structure
The voltage output from the DAC core is either converted to
a current (see Figure 64) which is then mirrored to the supply
rail so that the application simply sees a current source output
with respect to ground or it is buffered and scaled to output a
software selectable unipolar or bipolar voltage range (see
Figure 65). The current and voltage are output on separate
pins and cannot be output simultaneously.
12-/16-BIT
DAC
A1
AVDD
IOUT
A2
T1
T2
RSET
R2
R3
06
99
6-
0
5
8
Figure 64. Voltage-to-Current Conversion Circuitry
06
99
6-
0
59
12-/16-BIT
DAC
RANGE
SCALING
VCM
REFIN
+VSENSE
VOUT
–VSENSE
R1
RLOAD
–1V TO +3V
AD5412/AD5422
Figure 65. Voltage Output
Voltage Output Amplifier
The voltage output amplifier is capable of generating both
unipolar and bipolar output voltages. It is capable of driving
a load of 1 kΩ in parallel with 1 μF (with an external compen-
sation capacitor) to GND. The source and sink capabilities of
the output amplifier can be seen in Figure 35. The slew rate
is 1 V/μs with a full-scale settling time of 25 μs maximum (10 V
on top of a common-mode voltage (VCM) of 1 V to +3 V. In
output module applications where a cable could possibly
become disconnected from +VSENSE, resulting in the amplifier
loop being broken and possibly resulting in large destructive
voltages on VOUT, include an optional resistor (R1) between
2 kΩ and 5 kΩ to ensure the amplifier loop is kept closed. If
remote sensing of the load is not required, connect +VSENSE
directly to VOUT and connect VSENSE directly to GND. When
changing ranges on the voltage output, a glitch may occur. For
this reason, it is recommended that the output be disabled by
setting the OUTEN bit of the control register to logic low before
changing the output voltage range; this prevents a glitch from
occurring.
Driving Large Capacitive Loads
The voltage output amplifier is capable of driving capacitive
loads of up to 1 μF with the addition of a nonpolarized 4 nF
compensation capacitor between the CCOMP and VOUT pins.
Without the compensation capacitor, up to 20 nF capacitive
loads can be driven.
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