參數(shù)資料
型號(hào)： AD5439YRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 14/29頁(yè)
文件大小： 0K
描述： IC DAC DUAL 10BIT MULT 16-TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 96
設(shè)置時(shí)間： 35ns
位數(shù)： 10
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 3.5µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 2.47M
產(chǎn)品目錄頁(yè)面： 782 (CN2011-ZH PDF)
AD5429/AD5439/AD5449
Data Sheet
Rev. E | Page 20 of 28
SERIAL INTERFACE
The AD5429/AD5439/AD5449 have an easy-to-use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
most DSP interface standards. Data is written to the device in
16-bit words. Each 16-bit word consists of four control bits and
eight, 10, or 12 data bits, as shown in Figure 44 through Figure 46.
Low Power Serial Interface
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of SYNC. The SCLK and SDIN input buffers
are powered down on the rising edge of SYNC.
DAC Control Bit C3 to Control Bit C0
Control Bit C3 to Control Bit C0 allow control of various functions
of the DAC, as shown in Table 11. The default settings of the DAC
at power-on are such that data is clocked into the shift register
on falling clock edges and daisy-chain mode is enabled. The device
powers on with a zero-scale load to the DAC register and IOUT lines.
The DAC control bits allow the user to adjust certain features at
power-on. For example, daisy-chaining can be disabled if not in
use, an active clock edge can be changed to a rising edge, and DAC
output can be cleared to either zero scale or midscale. The user
can also initiate a readback of the DAC register contents for veri-
fication.
Control Register (Control Bits = 1101)
While maintaining software compatibility with single-channel
current output DACs (AD5426/AD5432/AD5443), these DACs
also feature additional interface functionality. Set the control bits
to 1101 to enter control register mode. Figure 47 shows the
contents of the control register, the functions of which are
described in the following sections.
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open-drain
driver. The strength of the SDO driver affects the timing of t12,
and, when stronger, allows a faster clock cycle.
Table 10. SDO Control Bits
SDO2
SDO1
Function Implemented
0
Full SDO driver
0
1
Weak SDO driver
1
0
SDO configured as open drain
1
Disable SDO output
Daisy-Chain Control (DSY)
DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode; a 0 disables daisy-chain mode.
When disabled, a readback request is accepted; SDO is auto-
matically enabled; the DAC register contents of the relevant
DAC are clocked out on SDO; and, when complete, SDO is
disabled again.
Hardware CLR Bit (HCLR)
The default setting for the hardware CLR bit is to clear the registers
and DAC output to zero code. A 1 in the HCLR bit allows the
CLR pin to clear the DAC outputs to midscale, and a 0 clears to
zero scale.
Active Clock Edge (SCLK)
The default active clock edge is a falling edge. Write a 1 to this
bit to clock data in on the rising edge, or a 0 to clock it in on the
falling edge.
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
DB0 (LSB)
DB15 (MSB)
04464-
013
Figure 44. AD5429 8-Bit Input Shift Register Contents
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
DB0 (LSB)
DB15 (MSB)
04464-
014
Figure 45. AD5439 10-Bit Input Shift Register Contents
DATA BITS
CONTROL BITS
C3
C2
C1
C0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
DB0 (LSB)
DB15 (MSB)
04464-
015
Figure 46. AD5449 12-Bit Input Shift Register Contents
CONTROL BITS
1
0
1
SDO2
SDO1
DSY
HCLR
SCLK
X
DB0 (LSB)
DB15 (MSB)
04464-
016
Figure 47. Control Register Loading Sequence
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