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參數(shù)資料
型號(hào)： AD5441BRMZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/17頁(yè)
文件大小： 0K
描述： IC DAC 12BIT SERIAL IN 8MSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 500ns
位數(shù)： 12
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 55µW
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電流，單極；1 電流，雙極
采樣率（每秒）： 5M
配用： EVAL-AD5541/42EBZ-ND - BOARD EVAL FOR AD5441/2
AD5441
Rev. A | Page 12 of 16
BIPOLAR 4-QUADRANT MULTIPLYING
Figure 24 shows a suggested circuit to achieve 4-quadrant
multiplying operation. The summing amplifier multiplies VOUT1
by 2 and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places VOUT2 at 0 V. The negative
full-scale voltage is VREF when the DAC is loaded with all zeros.
The positive full-scale output is (VREF 1 LSB) when the DAC
is loaded with all ones. Therefore, the digital coding is offset
binary. The voltage output transfer equation for various input
data and reference (or signal) values follows
VOUT2 = (D/2048 1) VREF
where:
D is the decimal data loaded into the DAC register.
VREF is the externally applied reference voltage source.
INTERFACE LOGIC INFORMATION
The AD5441 has been designed for ease of operation. The
timing diagram in Figure 2 illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
to the DAC register by taking LD momentarily low.
DIGITAL SECTION
The digital inputs of the AD5441, SRI, LD, and CLK, are TTL-
compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (VIN) passes through the transition region. See
for the supply current vs. logic input voltage graph. Maintaining
the digital input voltage levels as close as possible to the supplies,
VDD and GND, minimizes supply current consumption. The
digital inputs of the AD5441 were designed with ESD resistance
incorporated through careful layout and the inclusion of input
protection circuitry.
shows the input protection diodes
and series resistor; this input structure is duplicated on each
digital input. High voltage static charges applied to the inputs
are shunted to the supply and ground rails through forward-
biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.
VDD
LD, CLK, SRI
GND
5k
06
49
2-
0
2
0
Figure 23. Digital Input Protection
06
49
2-
0
24
NOTES
1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR VOUT = 0V WITH CODE 10000000 LOADED TO DAC.
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
RFB
IOUT1
GND
VREF
±10V
VREF
R1
AD5441
VDD
AGND
C1
A1
A2
R2
VOUT = –VREF TO +VREF
CONTROLLER
R3
20k
R4
10k
R5
20k
CLK
SRI
LD
Figure 24. Bipolar (4-Quadrant) Operation
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