參數(shù)資料
型號(hào): AD5450
廠商: Analog Devices, Inc.
英文描述: 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
中文描述: 8/10/12/14-Bit高帶寬倍增DAC的串行接口
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 125K
代理商: AD5450
AD5450/AD5451/AD5452/AD5453
5
REV. PrD
PRELIMINARY TECHNICAL DATA
PIN F UNC T ION D E SC R IPT ION
MSOP
T SOT
Mnemonic F unction
1
2
3
8
7
6
I
OU T
1
G N D
SC L K
DAC Current Output.
Ground Pin.
Serial Clock Input. By default, data is clocked into the input shift register on the
falling edge of the serial clock input. Alternatively, by means of the serial control
bits, the device may be configured such that data is clocked into the shift register on
the rising edge of SCLK .
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of
the serial clock input. By default, on power up, data is clocked into the shift register
on the falling edge of SCLK . T he control bits allow the user to change the active
edge to rising edge.
Active Low Control Input. T his is the frame synchronization signal for the input
data. Data is loaded to the shift register on the active edge of the
following clocks.
Positive power supply input. T hese parts can operate from a supply of +2.5 V to
+5.5 V.
DAC reference voltage input pin.
DAC feedback resistor pin. Establish voltage output for the DAC by connecting to
external amplifier output.
4
5
SD IN
5
4
S Y N C
6
3
V
D D
7
8
2
1
V
R E F
R
F B
PIN C ONF IGUR A T ION
AD5452/
AD5453
(Not to Scale)
IOUT1
GND
SCLK
SDIN
1
2
3
4
5
6
7
8 RFB
VREF
VDD
SYNC
AD5450/
AD5451/
AD5452/
AD5453
(Not to Scale)
IOUT1
GND
SCLK
SDIN
1
2
3
4
5
6
7
8
RFB
VREF
VDD
SYNC
MSOP (RM-8)
T SOT (UJ-8)
相關(guān)PDF資料
PDF描述
AD5451 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5452 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5452YRM 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5453 8/10/12/14-Bit High Bandwidth Multiplying DACs with Serial Interface
AD5450YUJ JACK, RJ45, R.ANG, PCB
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