參數(shù)資料
型號(hào): AD549KH
廠商: Analog Devices Inc
文件頁(yè)數(shù): 3/20頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP GP 1MHZ LP 20MA TO99-8
標(biāo)準(zhǔn)包裝: 1
系列: Topgate™
放大器類型: 通用
電路數(shù): 1
轉(zhuǎn)換速率: 3 V/µs
增益帶寬積: 1MHz
電流 - 輸入偏壓: 0.075pA
電壓 - 輸入偏移: 150µV
電流 - 電源: 600µA
電流 - 輸出 / 通道: 20mA
電壓 - 電源,單路/雙路(±): ±5 V ~ 18 V
工作溫度: 0°C ~ 70°C
安裝類型: 通孔
封裝/外殼: TO-99-8 金屬罐
供應(yīng)商設(shè)備封裝: TO-99-8
包裝: 散裝
AD549
Rev. H | Page 11 of 20
The case of the AD549 is connected to Pin 8 so that it can be
bootstrapped near the input potential. This minimizes pin
leakage and input common-mode capacitance due to the case.
Guard schemes for inverting and noninverting amplifier
topologies are illustrated in Figure 28 and Figure 29.
00
51
1
-02
8
2
3
6
8
AD549
+
VOUT
IN
CF
RF
GUARD
Figure 28. Inverting Amplifier with Guard
0
05
11
-0
29
3
2
6
8
AD549
+
VOUT
VS
+
GUARD
RF
RI
Figure 29. Noninverting Amplifier with Guard
Other guidelines include keeping the circuit layout as compact
as possible and keeping the input lines short. Keeping the assembly
rigid and minimizing sources of vibration reduces triboelectric
and piezoelectric effects. All precision, high impedance circuitry
requires shielding against interference noise. Use low noise coaxial
or triaxial cables for remote connections to the input signal lines.
OFFSET NULLING
The AD549 input offset voltage can be nulled by using balance
Pin 1 and Pin 5, as shown in Figure 30. Nulling the input offset
voltage in this fashion introduces an added input offset voltage
drift component of 2.4 μV/°C per mV of nulled offset (a maxi-
mum additional drift of 0.6 μV/°C for the AD549K, 1.2 μV/°C
for the AD549L, and 2.4 μV/°C for the AD549J).
00
51
1-
03
0
2
3
6
5
1
7
4
AD549
+
VOUT
–VS
+VS
10k
Figure 30. Standard Offset Null Circuit
The approach in Figure 31 can be used when the amplifier is
used as an inverter. This method introduces a small voltage
referenced to the power supplies in series with the positive
input terminal of the amplifier. The amplifier input offset
voltage drift with temperature is not affected. However,
variation of the power supply voltages causes offset shifts.
0
05
1
1-
03
1
2
3
6
AD549
+
VOUT
VI
+
RF
RI
200
100k
499k
0.1F
–VS
+VS
Figure 31. Alternate Offset Null Circuit for Inverter
Table 3. Insulating Materials and Characteristics
Material
Volume Resistivity
(V to CM)
Minimal
Triboelectric Effect1
Minimal
Piezoelectric Effect1
Resistance to
Water Absorption1
Teflon
1017 to 1018
W
G
Kel-F
1017 to 1018
W
M
G
Sapphire
1016 to 1018
M
G
Polyethylene
1014 to 1018
M
G
M
Polystyrene
1012 to 1018
W
M
Ceramic
1012 to 1014
W
M
W
Glass Epoxy
1010 to 1017
W
M
W
PVC
1010 to 1015
G
M
G
Phenolic
105 to 1012
W
G
W
1 G: good with regard to property; M: moderate with regard to property; W: weak with regard to property.
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