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參數(shù)資料
| 型號： | AD549LHZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP GP 1MHZ LP 20MA TO99-8 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Topgate™ |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 3 V/µs |
| 增益帶寬積： | 1MHz |
| 電流 - 輸入偏壓： | 0.04pA |
| 電壓 - 輸入偏移： | 300µV |
| 電流 - 電源： | 600µA |
| 電流 - 輸出 / 通道： | 20mA |
| 電壓 - 電源，單路/雙路(±)： | ±5 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | TO-99-8 金屬罐 |
| 供應(yīng)商設(shè)備封裝： | TO-99-8 |
| 包裝： | 散裝 |
| 產(chǎn)品目錄頁面： | 773 (CN2011-ZH PDF) |
AD549
Rev. H | Page 10 of 20
FUNCTIONAL DESCRIPTION
MINIMIZING INPUT CURRENT
The AD549 is optimized for low input current and offset
voltage. Careful attention to how the amplifier is used reduces
input currents in actual applications.
Keep the amplifier operating temperature as low as possible to
minimize input current. Like other JFET input amplifiers, the
AD549 input current is sensitive to chip temperature, rising by
a factor of 2.3 for every 10°C. Figure 25 is a plot of the AD549
input current vs. ambient temperature.
1nA
100pA
10pA
1pA
100fA
10fA
1fA
–55
–25
5
35
65
125
95
00
51
1-
0
25
TEMPERATURE (°C)
INP
U
T
BI
AS
CU
RRE
N
T
Figure 25. Input Bias Current vs. Ambient Temperature
On-chip power dissipation raises the chip operating tempera-
ture, causing an increase in input bias current. Due to the low
quiescent supply current of the AD549, the chip temperature
is less than 3°C higher than its ambient temperature when the
(unloaded) amplifier is operating with 15 V supplies. The
difference in the input current is negligible.
However, heavy output loads can cause a significant increase in
chip temperature and a corresponding increase in the input
current. Maintaining a minimum load resistance of 10 Ω is
recommended. Input current vs. additional power dissipation
due to output drive current is plotted in Figure 26.
6
5
4
3
2
1
0
25
50
75
100
125
150
175
200
00
51
1-
0
26
ADDITIONAL INTERNAL POWER DISSIPATION (mW)
NO
RM
AL
IZ
E
D
I
NP
UT
B
IA
S
CURR
E
NT
BASED ON
TYPICAL IB = 40fA
Figure 26. Input Bias Current vs. Additional Power Dissipation
CIRCUIT BOARD NOTES
A number of physical phenomena generate spurious currents
that degrade the accuracy of low current measurements. Figure 27
is a schematic of a current to voltage (I-to-V) converter with
these parasitic currents modeled.
00
51
1-
02
7
2
3
6
8
AD549
+
VOUT
–
fS
CF
RF
VS
RP
CP
II' =
+V +
CP
V
RP
dCP
dT
dV
dT
Figure 27. Sources of Parasitic Leakage Currents
Finite resistance from input lines to voltages on the board,
modeled by Resistor RP, results in parasitic leakage. Insulation
resistance of more than 1015 Ω must be maintained between
the amplifier signal and supply lines to capitalize on the low
input currents of the AD549. Standard PCB material does not
have high enough insulation resistance; therefore, connect the
input leads of the AD549 to standoffs made of insulating
material with adequate volume resistivity (that is, Teflon). The
surface of the insulator must be kept clean to preserve surface
resistivity. For Teflon, an effective cleaning procedure consists
of swabbing the surface with high grade isopropyl alcohol,
rinsing with deionized water, and baking the board at 80°C for
10 minutes.
In addition to high volume and surface resistivity, other proper-
ties are desirable in the insulating material chosen. Resistance
to water absorption is important because surface water films
drastically reduce surface resistivity. The insulator chosen
should also exhibit minimal piezoelectric effects (charge
emission due to mechanical stress) and triboelectric effects
(charge generated by friction). Charge imbalances generated
by these mechanisms can appear as parasitic leakage currents.
These effects are modeled by Variable Capacitor CP in Figure 27.
Guarding the input lines by completely surrounding them with
a metal conductor biased near the potential of the input lines
has two major benefits. First, parasitic leakage from the signal
line is reduced because the voltage between the input line and
the guard is very low. Second, stray capacitance at the input
node is minimized. Input capacitance can substantially degrade
signal bandwidth and the stability of the I-to-V converter.
1 Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland,
Ohio, 1977.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD549LHZ | 制造商:Analog Devices 功能描述:IC, OP-AMP, 1MHZ, 3V/ us, TO-99-8 |
| AD549S | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultralow Input Bias Current Operational Amplifier |
| AD549SH | 制造商:Analog Devices 功能描述: |
| AD549SH/883B | 制造商:Analog Devices 功能描述:OP Amp Single GP 制造商:Analog Devices 功能描述:OP AMP SGL GP 18V 8PIN TO-99 - Rail/Tube 制造商:Analog Devices 功能描述:ULTRALOW BIAS CURRENT AMP 制造商:Rochester Electronics LLC 功能描述:ULTRALOW BIAS CURRENT AMP - Bulk 制造商:Analog Devices 功能描述:IC OP-AMP CURRENT ULTRALOW BIAS 制造商:Analog Devices Inc. 功能描述:Precision Amplifiers ULTRALOW BIAS CURRENT AMP 制造商:Analog Devices Inc. 功能描述:Precision Amplifiers IC ULTRALOW BIAS CURRENT |
| AD-55 | 制造商:MEANWELL 制造商全稱:Mean Well Enterprises Co., Ltd. 功能描述:55W Single Output with Battery Charger(UPS Function) |
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