參數資料
型號： AD5522JSVUZ
廠商： Analog Devices Inc
文件頁數： 2/64頁
文件大?。?/td> 0K
描述： IC PMU QUAD 16BIT DAC 80-TQFP
產品變化通告： Improve FI ac crosstalk
設計資源： Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
標準包裝： 1
類型： 每引腳參數測量單元（PPMU）
應用： 自動測試設備
安裝類型： 表面貼裝
封裝/外殼： 80-TQFP 裸露焊盤
供應商設備封裝： 80-TQFP-EP（12x12）
包裝： 托盤
AD5522
Data Sheet
Rev. E | Page 10 of 64
Parameter
Min
Max
Unit
Test Conditions/Comments
DIE TEMPERATURE SENSOR
Accuracy2
±7
°C
Output Voltage at 25°C
1.5
V
Output Scale Factor2
4.6
mV/°C
Output Voltage Range2
0
3
V
INTERACTION AND CROSSTALK2
DC Crosstalk (FOHx)
0.05
0.65
mV
DC change resulting from a dc change in any DAC
in the device, FV and FI modes, ±2 mA range,
CLOAD = 200 pF, RLOAD = 5.6 kΩ
DC Crosstalk (MEASOUTx)
0.05
0.65
mV
DC change resulting from a dc change in any DAC
in the device, MV and MI modes, ±2 mA range,
CLOAD = 200 pF, RLOAD = 5.6 kΩ
DC Crosstalk Within a Channel
0.05
mV
All channels in FVMI mode, one channel at midscale;
measure the current for one channel in the lowest
current range for a change in comparator or clamp
DAC levels for that PMU
SPI INTERFACE LOGIC INPUTS
Input High Voltage, VIH
1.7/2.0
V
(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant
input levels
Input Low Voltage, VIL
0.7/0.8
V
(2.3 V to 2.7 V)/(2.7 V to 5.25 V), JEDEC-compliant
input levels
Input Current, IINH, IINL
1
+1
A
Input Capacitance, CIN2
10
pF
CMOS LOGIC OUTPUTS
SDO, CPOx
Output High Voltage, VOH
DVCC 0.4
V
Output Low Voltage, VOL
0.4
V
IOL = 500 A
Tristate Leakage Current
2
+2
A
SDO, CPOH1/SDO
1
+1
A
All other output pins
Output Capacitance2
10
pF
OPEN-DRAIN LOGIC OUTPUTS
BUSY, TMPALM, CGALM
Output Low Voltage, VOL
0.4
V
IOL = 500 A, CLOAD = 50 pF, RPULLUP = 1 kΩ
Output Capacitance2
10
pF
LVDS INTERFACE LOGIC INPUTS
REDUCED RANGE LINK2
Input Voltage Range
875
1575
mV
Input Differential Threshold
100
+100
mV
External Termination Resistance
80
100
120
Ω
Differential Input Voltage
100
mV
LVDS INTERFACE LOGIC OUTPUTS
REDUCED RANGE LINK
Output Offset Voltage
1200
mV
Output Differential Voltage
400
mV
POWER SUPPLIES
AVDD
10
28
V
|AVDD AVSS| ≤ 33 V
AVSS
23
5
V
DVCC
2.3
5.25
V
AIDD
26
mA
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard disabled
AISS
26
mA
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard disabled
AIDD
28
mA
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard enabled
AISS
28
mA
Internal ranges (±5 μA to ±2 mA), excluding load
conditions; comparators and guard enabled
AIDD
36
mA
External range, excluding load conditions
AISS
36
mA
External range, excluding load conditions
DICC
1.5
mA
Maximum Power Dissipation2
7
W
Maximum power that should be dissipated in this
package under worst-case load conditions; careful
consideration should be given to supply selection
and thermal design
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