參數(shù)資料
型號(hào)： AD5531
廠商： Analog Devices, Inc.
英文描述： Serial Input, Voltage Output 12-/14-Bit DACs
中文描述： 串行輸入，電壓輸出數(shù)模轉(zhuǎn)換器12-/14-Bit
文件頁(yè)數(shù)： 3/16頁(yè)
文件大?。?/td> 407K
代理商： AD5531
REV. 0
AD5530/AD5531
–3–
Parameter
AD5530
AD5531
Unit
Test Conditions/Comments
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Error
Gain Error
Gain Temperature Coefficient
2
12
±
1
±
1
±
2
±
2
±
1
0.5
10
14
±
2
±
1
±
8
±
8
±
4
0.5
10
Bits
LSB max
LSB max
LSB max
LSB max
LSB typ
ppm FSR/
°
C typ
ppm FSR/
°
C max
Guaranteed Monotonic Over Temperature
Typically within
±
1 LSB
Typically within
±
1 LSB
REFERENCE INPUTS
2
Reference Input Range
DC Input Resistance
Input Current
DUTGND INPUT
2
DC Input Impedance
Max Input Current
Input Range
O/P CHARACTERISTICS
2
Output Voltage Swing
Short Circuit Current
Resistive Load
Capacitive Load
DC Output Impedance
0/4.096
100
±
1
0/4.096
100
±
1
V min/V max
M
typ
μ
A max
Max Output Range
±
8.192 V
Per Input. Typically
±
20 nA.
60
±
0.3
–
3/+3
60
±
0.3
–
3/+3
k
typ
mA typ
V min/V max
Max Output Range
±
8.192 V
±
8.192
15
5
1200
0.5
±
8.192
15
5
1200
0.5
V max
mA max
k
min
pF max
max
To 0 V
To 0 V
DIGITAL I/O
V
INH
, Input High Voltage
V
INL
, Input Low Voltage
I
INH
, Input Current
C
IN
, Input Capacitance
2
SDO V
OL
Output Low Voltage
POWER REQUIREMENTS
V
DD
/V
SS
Power Supply Sensitivity
Full Scale/
V
DD
Full Scale/
V
SS
I
DD
I
SS
I
DD
in Power-Down
2.4
0.8
±
10
10
0.4
2.4
0.8
±
10
10
0.4
V min
V max
μ
A max
pF max
V max
Total for All Pins
3 pF Typ
I
SINK
= 1 mA
+12/
–
12
+12/
–
12
V nom
±
10% For Specified Performance
110
100
2
2
150
110
100
2
2
150
dB typ
dB typ
mA max
mA max
μ
A max
Outputs Unloaded
Outputs Unloaded
Typically 50
μ
A
NOTES
1
Temperature range for B Version:
–
40
°
C to +85
°
C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS
Parameter
A
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
20
μ
s typ
Full-Scale Change to
±
1/2 LSB. DAC Latch Contents
alternately loaded with all 0s and all 1s.
Slew Rate
Digital-to-Analog Glitch Impulse
1.3
120
V/
μ
s typ
nV-s typ
DAC Latch alternately loaded with 0FFF Hex and
1000 Hex. Not dependent on load conditions.
Effect of Input Bus Activity on DAC Output Under Test
Digital Feedthrough
Output Noise Spectral Density
@ 1 kHz
0.5
nV-s typ
100
nV/(Hz)
1/2
typ
All 1s Loaded to DAC
Specifications subject to change without notice. Guaranteed by design, not subject to production test.
SPECIFICATIONS
1
(V
DD
= +12 V
±
10%; V
SS
= –12 V
±
10%; GND = 0 V;
R
L
= 5 k
and C
L
= 220 pF to GND; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
(V
DD
= 10.8 V to 16.5 V, V
SS
= –10.8 V to –16.5 V; GND = 0 V; R
L
= 5 k
and
C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
相關(guān)PDF資料
PDF描述
AD5531BRU RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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