參數(shù)資料
型號: AD5531BRU
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 05V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85%
中文描述: SERIAL INPUT LOADING, 20 us SETTLING TIME, 14-BIT DAC, PDSO16
封裝: MO-153AB, TSSOP-16
文件頁數(shù): 4/16頁
文件大?。?/td> 407K
代理商: AD5531BRU
REV. 0
–4–
AD5530/AD5531
STANDALONE TIMING CHARACTERISTICS
1, 2
(V
DD
= 10.8 V to 16.5 V, V
SS
= –10.8 V to –16.5 V; GND = 0 V;
R
L
= 5 k
and C
L
= 220 pF to GND. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
SCLK
SYNC
SDIN
LDAC
*
CLR
*
LDAC
MAY BE TIED PERMANENTLY LOW IF REQUIRED
t
1
DB15
DB14
DB11
DB0
MSB
LSB
t
4
t
6
t
7
t
8
t
12
t
9
t
10
t
11
t
5
t
3
t
2
Figure 1. Timing Diagram for Standalone Mode
Parameter
Limit at T
MIN
, T
MAX
7
140
60
60
50
40
50
40
15
5
50
5
50
Unit
Description
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Frequency
SCLK Cycle Time
SCLK Low Time
SCLK High Time
SYNC
to SCLK Falling Edge Setup Time
SCLK Falling Edge to
SYNC
Rising Edge
Min
SYNC
High Time
Data Setup Time
Data Hold Time
SYNC
High to
LDAC
Low
LDAC
Pulsewidth
LDAC
High to
SYNC
Low
CLR
Pulsewidth
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+V
IH
)/2.
Specifications subject to change without notice.
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