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參數(shù)資料
| 型號： | AD5531BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT SRL IN/VOUT 16TSSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 20µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 60mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，雙極 |
| 采樣率（每秒）： | 50k |
AD5530/AD5531
Rev. B | Page 5 of 20
AC PERFORMANCE CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = 10.8 V to 16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 3.
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
20
μs typ
Full-scale change to ± LSB. DAC latch contents alternately
loaded with all 0s and all 1s.
Slew Rate
1.3
V/μs typ
Digital-to-Analog Glitch Impulse
120
nV-s typ
DAC latch alternately loaded with 0x0FFF and 0x1000. Not
dependent on load conditions.
Digital Feedthrough
0.5
nV-s typ
Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 1 kHz
100
nV/√Hz typ
All 1s loaded to DAC.
STANDALONE TIMING CHARACTERISTICS
VDD = 10.8 V to 16.5 V, VSS = 10.8 V to 16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications TMIN to TMAX, unless
otherwise noted.
Table 4.
Parameter
Limit at TMIN, TMAX
Unit
Description
fMAX
7
MHz max
SCLK frequency
t1
140
ns min
SCLK cycle time
t2
60
ns min
SCLK low time
t3
60
ns min
SCLK high time
t4
50
ns min
SYNC to SCLK falling edge setup time
t5
40
ns min
SCLK falling edge to SYNC rising edge
t6
50
ns min
Min SYNC high time
t7
40
ns min
Data setup time
t8
15
ns min
Data hold time
t9
5
ns min
SYNC high to LDAC low
t10
50
ns min
LDAC pulse width
t11
5
ns min
LDAC high to SYNC low
t12
50
ns min
CLR pulse width
1 Guaranteed by design, not subject to production test.
2 Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
SCLK
SYNC
SDIN
MSB
DB15
DB14
DB11
DB0
LSB
t1
t3
t2
t5
t4
t6
t7
t8
t9
t10
t11
t12
LDAC1
CLR
1LDAC CAN BE TIED PERMANENTLY LOW, IF REQUIRED.
0
09
38
-0
02
Figure 2. Timing Diagram for Standalone Mode
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