參數(shù)資料
型號(hào)： AD5532ABC-2
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 32-Channel Infinite Sample-and-Hold
中文描述： SERIAL INPUT LOADING, 30 us SETTLING TIME, 14-BIT DAC, PBGA74
封裝： 12 X 12 MM, MO-192ABD-1, CSPBGA-74
文件頁(yè)數(shù)： 13/16頁(yè)
文件大?。?/td> 244K
代理商： AD5532ABC-2
REV. 0
AD5532
–13–
OFFSET SEL
A4
–
A0
CAL
0
0
MSB
LSB
MODE BIT 1
MODE BIT 2
MODE BITS
0
TEST BIT
a. 10-Bit Input Serial Write Word (SHA Mode)
OFFSET SEL
A4
–
A0
CAL
1
0
MSB
LSB
MODE BITS
DB13
–
DB0
0
TEST BIT
b. 24-Bit Input Serial Write Word (DAC Mode)
OFFSET SEL
A4
–
A0
CAL
0
1
MSB
LSB
MODE BITS
DB13
–
DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
c. Input Serial Interface (Acquire and Readback Mode)
OFFSET SEL
A4
–
A0
CAL
1
1
MSB
LSB
MODE BITS
DB13
–
DB0
0
TEST BIT
10-BIT
SERIAL WORD
WRITTEN TO PART
14-BIT DATA
READ FROM PART AFTER
NEXT FALLING EDGE OF
SYNC
(DB13 = MSB OF DAC WORD)
MSB
LSB
d. Input Serial Interface (Readback Mode)
Figure 19. Serial Interface Formats
DB13–DB0
These are used to write a 14-bit word into the addressed DAC
register. Clearly, this is only valid when in DAC mode.
The serial interface is designed to allow easy interfacing to
most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI,
SPI, DSP56000, TMS320, and ADSP-21xx, without the need
for any glue logic. When interfacing to the 8051, the SCLK
must be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.
Figures 3, 4, and 5 show the timing diagram for a serial read and
write to the AD5532. The serial interface works with both a con-
tinuous and a noncontinuous serial clock. The first falling edge of
SYNC
resets a counter that counts the number of serial clocks to
ensure the correct number of bits are shifted in and out of the
serial shift registers. Any further edges on
SYNC
are ignored until
the correct number of bits are shifted in or out. Once the correct
number of bits for the selected mode have been shifted in or out,
the SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of
SYNC
.
In readback, the first rising SCLK edge after the falling edge of
SYNC
causes D
OUT
to leave its high impedance state and data
is clocked out onto the D
OUT
line and also on subsequent SCLK
rising edges. The D
OUT
pin goes back into a high impedance
state on the falling edge of the fourteenth SCLK. Data on the
D
IN
line is latched in on the first SCLK falling edge after the
falling edge of the
SYNC
signal and on subsequent SCLK fall-
ing edges. During readback D
IN
is ignored. The serial interface
will not shift data in or out until it receives the falling edge of
the
SYNC
signal.
Parallel Interface (SHA Mode Only)
The SER/
PAR
bit must be tied low to enable the parallel inter-
face and disable the serial interface. The parallel interface is
controlled by 9 pins.
CS
Active low package select pin. This pin is shared with the
SYNC
function for the serial interface.
WR
Active low write pin. The values on the address pins are latched
on a rising edge of
WR
.
A4–A0
Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).
Offset_Sel
Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed. The address on A4–A0 is ignored in this case.
Cal
When this pin is high, all 32 channels acquire V
IN
simultaneously.
The acquisition time is then 45
μ
s (typ) and accuracy may be
reduced.
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