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參數(shù)資料
| 型號： | AD5532B |
| 英文描述： | AD5532B: 32-Channel. 14-Bit DAC with Precision Infinite Sample-and-Hold Mode (Rev A. 9/02) |
| 中文描述： | AD5532B：32通道。 14位的采樣精度無限援和持有模式（活答：9月2日） |
| 文件頁數(shù)： | 8/16頁 |
| 文件大?。?/td> | 569K |
| 代理商： | AD5532B |
REV. A
AD5532B
–8–
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
AGND (1–2)
AV
CC
(1–2)
V
DD
(1–4)
V
SS
(1–4)
DGND
DV
CC
DAC_GND (1–2)
REF_IN
REF_OUT
V
OUT
(0–31)
V
IN
A4–A1
1
, A0
2
CAL
1
CS
/
SYNC
Analog GND Pins
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
V
DD
Supply Pins. Voltage range from 8 V to 16.5 V.
V
SS
Supply Pins. Voltage range from –4.75 V to –16.5 V.
Digital GND Pins
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for all the DACs
Reference Voltage for Channels 0–31
Reference Output Voltage
Analog Output Voltages from the 32 Channels
Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface. 5-address pins for 32 channels. A4 = MSB of channel address. A0 = LSB.
Parallel Interface. Control input that allows all 32 channels to acquire V
IN
simultaneously.
This pin is both the active low chip select pin for the parallel interface and the frame synchronization pin for
the serial interface.
Parallel Interface. Write pin. Active low. This is used in conjunction with the
CS
pin to address the device
using the parallel interface.
Parallel Interface. Offset select pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
Output from the DAC Registers for Readback. Data is clocked out on the rising edge of SCLK and is valid
on the falling edge of SCLK.
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,
the parallel interface will be used. If it is tied high, the serial interface will be used.
Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to
this pin if the user wants to drive this pin with the offset channel.
Offset Output. This is the acquired/programmed offset voltage that can be tied to OFFS_IN to offset the span.
This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns
high when the acquisition operation is complete.
If this input is held high, V
IN
is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to V
IN
. The addressed channel begins to acquire V
IN
on the rising edge
of
TRACK
. See
TRACK
Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low going
pulse of between 90 ns and 200 ns to this pin. See section on
RESET
Function for further details.
WR
1
OFFSET_SEL
1
SCLK
2
D
IN2
D
OUT
SER/
PAR
1
OFFS_IN
OFFS_OUT
BUSY
TRACK
/
RESET
2
NOTES
1
Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.
2
Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.
IDEAL TRANSFER
FUNCTION
IDEAL GAIN REFIN
DAC CODE
OUTPUT
VOLTAGE
IDEAL GAIN 50mV
0
16k
FULL-SCALE
ERROR RANGE
OFFSET
RANGE
Figure 6. DAC Transfer Function (OFFS_IN = 0)
2.96 3V
70mV
0V
V
OUT
IDEAL
TRANSFER
FUNCTION
ACTUAL
TRANSFER
FUNCTION
OFFSET
ERROR
GAIN ERROR +
OFFSET ERROR
V
IN
UPPER
DEAD BAND
LOWER
DEAD BAND
Figure 7. ISHA Transfer Function
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