- 您現在的位置：買賣IC網 > PDF目錄362093 > AD5532BBC-1 SAMPLE/TRACK-AND-HOLD AMPLIFIER|32-CHANNEL|CMOS|BGA|74PIN|PLASTIC PDF資料下載
參數資料
| 型號： | AD5532BBC-1 |
| 元件分類： | 取樣保持放大器 |
| 英文描述： | SAMPLE/TRACK-AND-HOLD AMPLIFIER|32-CHANNEL|CMOS|BGA|74PIN|PLASTIC |
| 中文描述： | 采樣/跟蹤和保持放大器| 32-CHANNEL |的CMOS | BGA封裝| 74PIN |塑料 |
| 文件頁數： | 14/16頁 |
| 文件大?。?/td> | 569K |
| 代理商： | AD5532BBC-1 |
REV. A
AD5532B
–14–
MICROPROCESSOR INTERFACING
AD5532B to ADSP-21xx Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5532B without the need for extra logic.
A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532B on the falling edge of its SCLK.
In readback, 16 bits of data are clocked out of the AD5532B on
each rising edge of SCLK and clocked into the DSP on the
rising edge of SCLK. D
IN
is ignored. The valid 14 bits of data
will be centered in the 16-bit RX register when using this configu-
ration. The SPORT control register should be set up as follows:
TFSW
= RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK
= 1, Internal Serial Clock
TFSR
= RFSR = 1, Frame Every Word
IRFS
= 0, External Framing Signal
ITFS
= 1, Internal Framing Signal
SLEN
= 1001, 10-Bit Data-Words (ISHA Mode Write)
SLEN
= 0111, 3 8-Bit Data-Words (DAC Mode Write)
SLEN
= 1111, 16-Bit Data-Words (Readback Mode)
Figure 11 shows the connection diagram.
SCLK
AD5532B
*
D
OUT
SYNC
D
IN
DR
TFS
RFS
DT
SCLK
ADSP-2101/
ADSP-2103
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 11. AD5532B to ADSP-2101/ADSP-2103 Interface
AD5532B to MC68HC11
The serial peripheral interface (SPI) on the MC68HC11 is confi-
gured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0,
and the clock phase bit (CPHA) = 1. The SPI is configured by
writing to the SPI control register (SPCR)—see
68HC11 User
Manual
. SCK of the 68HC11 drives the SCLK of the AD5532B, the
MOSI output drives the serial data line (D
IN
) of the AD5532B,
and the MISO input is driven from D
OUT
. The
SYNC
signal is
derived from a port line (PC7). A connection diagram is shown
in Figure 12.
SCLK
AD5532B
*
D
OUT
SYNC
D
IN
MISO
PC7
SCK
MC68HC11
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
MOSI
Figure 12. AD5532B to MC68HC11 Interface
When data is being transmitted to the AD5532B, the SYNC line
is taken low (PC7). Data appearing on the MOSI output is valid
on the falling edge of SCK. Serial data from the 68HC11 is
transmitted in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first. In
order to transmit 10 data bits in ISHA mode, it is important to
left-justify the data in the SPDR register. PC7 must be pulled
low to start a transfer. It is taken high and pulled low again before
any further read/write cycles can take place.
AD5532B to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured as
an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
See
PIC16/17 Microcontroller User Manual
. In this example,
I/O port RA1 is being used to pulse
SYNC
and enable the serial
port of the AD5532B. This microcontroller transfers only eight
bits of data during each serial transfer operation; therefore, two or
three consecutive read/write operations are needed depending
on the mode. Figure 13 shows the connection diagram.
SCLK
PIC16C6x/7x
*
D
OUT
D
IN
SYNC
SCK/RC3
AD5532B
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
SDO/RC5
SDI/RC4
RA1
Figure 13. AD5532B to PIC16C6x/7x Interface
AD5532B to 8051
The AD5532B requires a clock synchronized to the serial data. The
8051 serial interface must therefore be operated in Mode0. In this
mode, serial data enters and exits through RxD and a shift clock
is output on TxD. Figure 14 shows how the 8051 is connected
to the AD5532B. Because the AD5532B shifts data out on the
rising edge of the shift clock and latches data in on the falling
edge, the shift clock must be inverted. The AD5532B requires its
data with the MSB first. Since the 8051 outputs the LSB first,
the transmit routine must take this into account.
8051
*
SCLK
D
OUT
SYNC
D
IN
TxD
AD5532B
*
*
ADDITIONAL PINS OMITTED FOR CLARITY
RxD
P1.1
Figure 14. AD5532B to 8051 Interface
相關PDF資料 |
PDF描述 |
|---|---|
| AD5539 | Ultrahigh Frequency Operational Amplifier(487.53 k) |
| AD5539JN | Voltage-Feedback Operational Amplifier |
| AD5539JQ | Voltage-Feedback Operational Amplifier |
| AD5539SQ | Voltage-Feedback Operational Amplifier |
| AD5564B | Industrial Control IC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD5532BBCZ-1 | 功能描述:IC DAC 14BIT 32CH BIPO 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 標準包裝:1 系列:- 設置時間:4.5µs 位數:12 數據接口:串行，SPI? 轉換器數目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5532HS | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| AD5532HSABC | 功能描述:IC DAC 14BIT 32CH 74-CSPBGA RoHS:否 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5532HSABCZ | 功能描述:IC DAC 14BIT 32CH HS 74-CSPBGA RoHS:是 類別:集成電路 (IC) >> 數據采集 - 數模轉換器 系列:- 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數:8 數據接口:串行 轉換器數目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數目和類型:8 電壓，單極 采樣率（每秒）:* |
| AD5533 | 制造商:AD 制造商全稱:Analog Devices 功能描述:32-Channel Infinite Sample-and-Hold |
發(fā)布緊急采購，3分鐘左右您將得到回復。