VREF_IN

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    參數(shù)資料
    型號(hào): AD5532HSABC
    廠商: Analog Devices Inc
    文件頁(yè)數(shù): 10/12頁(yè)
    文件大小: 0K
    描述: IC DAC 14BIT 32CH 74-CSPBGA
    產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
    DAC Architectures
    標(biāo)準(zhǔn)包裝: 1
    設(shè)置時(shí)間: 10µs
    位數(shù): 14
    數(shù)據(jù)接口: 串行
    轉(zhuǎn)換器數(shù)目: 34
    電壓電源: 模擬和數(shù)字
    功率耗散(最大): 623mW
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 74-LBGA,CSPBGA
    供應(yīng)商設(shè)備封裝: 74-CSPBGA(12x12)
    包裝: 托盤
    輸出數(shù)目和類型: 32 電壓,單極
    采樣率(每秒): 1.1M
    配用: EVAL-AD5532HSEBZ-ND - BOARD EVAL FOR AD5532HS
    EVAL-AD5532EBZ-ND - BOARD EVAL FOR AD5532
    REV. 0
    AD5532HS
    –7–
    Typical Performance Characteristics–
    DAC CODE
    D
    A
    C
    ERR
    OR
    –LSBs
    1.0
    0
    VREF_IN = 2.5V
    VOFFS_IN = 0V
    TA = 25 C
    2K
    4K
    6K
    8K
    10K 12K 14K16K
    0.8
    0.6
    0.4
    0.2
    0.0
    –0.2
    –0.4
    –0.6
    –0.8
    –1.0
    TPC 1. Typical DNL Plot
    SINK/SOURCE CURRENT – mA
    V
    OUT
    V
    2.535
    2.530
    2.520
    64
    20
    2.525
    TA = 25 C
    VREFIN = 2.5V
    VOFFS_IN = 0V
    DAC LOADED TO MIDSCALE
    –2
    –4
    –6
    TPC 4. VOUT Source and Sink
    Capability
    % FSR
    FREQ
    UENCY
    %
    15
    10
    0
    0.1
    5
    0.2
    0.3
    TPC 7. INL Error Distribution at 25
    °C
    DNL
    ERR
    OR
    LSBs
    1.0
    –40
    040
    80
    0.5
    0.0
    –0.5
    –1.0
    INL
    ERR
    OR
    %
    FSR
    0.2
    0.1
    0.0
    –0.1
    –0.2
    TEMPERATURE – C
    DNL MIN
    INL MIN
    INL MAX
    DNL MAX
    TPC 2. INL Error and DNL Error vs.
    Temperature
    V
    OUT
    V
    –1
    1
    2
    3
    4
    5
    6
    0
    TA = 25 C
    VREFIN = 2.5V
    VOFFS_IN = 0V
    TIME BASE – 1.25 s/DIV
    TPC 5. Full-Scale Settling Time
    mV
    FREQ
    UENCY
    %
    15
    10
    0
    10
    30
    5
    20
    TPC 8. Offset Error Distribution
    at 25
    °C
    TEMPERATURE – C
    V
    OUT
    V
    5.000
    4.995
    4.985
    –40
    0
    40
    80
    4.990
    VREFIN = 2.5V
    VOFFS_IN = 0V
    DAC LOADED TO FULL SCALE
    TPC 3. VOUT vs. Temperature
    TIME BASE – 200ns/DIV
    V
    OUT
    V
    2.494
    2.506
    2.508
    2.510
    2.512
    2.514
    2.516
    2.518
    2.520
    TA = 25 C
    VREFIN = 2.5V
    VOFFS_IN = 0V
    2.498
    2.500
    2.502
    2.504
    2.496
    TPC 6. Major Code Transition Glitch
    Impulse
    % FSR
    FREQ
    UENCY
    %
    20
    10
    0
    –1.0
    –0.5
    0.0
    TPC 9. Full-Scale Error Distribution
    at 25
    °C
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