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參數(shù)資料
| 型號： | AD5533 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RE Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 12V; Output Voltage (Vdc): 12V; Power: 1W; Industry Standard Pinout; 1kVDC & 2kVDC Isolation; UL94V-0 Package Material; Optional Continuous Short Circuit Protected; Fully Encapsulated; Custom Solutions Available; Efficiency to 85% |
| 中文描述： | 32通道無限采樣保持 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 224K |
| 代理商： | AD5533 |
AD5533
TIMING CHARACTERISTICS
PARALLEL INTERFACE
–4–
REV. 0
Limit at T
MIN
, T
MAX
(A Version)
Parameter
1, 2
Unit
Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
0
0
50
50
20
0
ns min
ns min
ns min
ns min
ns min
ns min
CS
to
WR
Setup Time
CS
to
WR
Hold Time
CS
Pulsewidth Low
WR
Pulsewidth Low
A4–A0, CAL, OFFS_SEL to
WR
Setup Time
A4–A0, CAL, OFFS_SEL to
WR
Hold Time
NOTES
1
See Interface Timing Diagram.
2
Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
SERIAL INTERFACE
Limit at T
MIN
, T
MAX
(A Version)
Parameter
1, 2
Unit
Conditions/Comments
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
83
t
93
t
10
20
20
20
10
50
10
5
5
20
60
400
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC
Falling Edge to SCLK Falling Edge Setup Time
SYNC
Low Time
D
IN
Setup Time
D
IN
Hold Time
SYNC
Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to D
OUT
Valid
SCLK Falling Edge to D
OUT
High Impedance
10th SCLK Falling Edge to
SYNC
Falling Edge for Readback
NOTES
1
See Serial Interface Timing Diagrams.
2
Guaranteed by design and characterization, not production tested.
3
These numbers are measured with the load circuit of Figure 2.
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAM
CS
WR
A4
–
A0, CAL,
OFFS SEL
Figure 1. Parallel Write (SHA Mode Only)
I
OL
200 A
I
OH
200 A
C
50pF
TO
OUTPUT
PIN
1.6V
Figure 2. Load Circuit for D
OUT
Timing Specifications
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