- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8597 > AD5541LRZ-REEL7 (Analog Devices Inc)IC DAC 16BIT SRL IN/VOUT 8-SOIC PDF資料下載
參數(shù)資料
| 型號： | AD5541LRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT SRL IN/VOUT 8-SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169) |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 設(shè)置時(shí)間： | 1µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 825µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | 1.5M |
AD5541/AD5542
Data Sheet
Rev. F | Page 4 of 20
Min
Typ
Max
Unit
Test Conditions
POWER REQUIREMENTS
Digital inputs at rails
VDD
2.7
5.5
V
IDD
125
150
μA
Power Dissipation
0.625
0.825
mW
1 Temperature ranges are as follows: A, B, C versions: 40°C to +85°C; J, L versions: 0°C to 70°C.
2 Reference input resistance is code-dependent, minimum at 0x8555.
3 Guaranteed by design, not subject to production test.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V ±10%, VREF= 2.5 V, VINH = 3 V and 90% of VDD, VINL = 0 V and 10% of VDD, AGND = DGND = 0 V; 40°C < TA <
+85°C, unless otherwise noted.
Table 3.
Parameter1, 2
Limit
Unit
Description
f
SCLK
25
MHz max
SCLK cycle frequency
t
1
40
ns min
SCLK cycle time
t
2
20
ns min
SCLK high time
t
3
20
ns min
SCLK low time
t
4
10
ns min
CS low to SCLK high setup
t
5
15
ns min
CS high to SCLK high setup
t
6
30
ns min
SCLK high to CS low hold time
t
7
20
ns min
SCLK high to CS high hold time
t
8
15
ns min
Data setup time
t
9
4
ns min
Data hold time (V
INH = 90% of VDD, VINL = 10% of VDD)
t
9
7.5
ns min
Data hold time (V
INH = 3V, VINL = 0 V)
t
10
30
ns min
LDAC pulse width
t
11
30
ns min
CS high to LDAC low setup
t
12
30
ns min
CS high time between active periods
1 Guaranteed by design and characterization. Not production tested
2 All input signals are specified with t
R = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
SCLK
CS
DIN
DB15
LDAC*
t6
t4
t12
t8
t5
t2
t3
t1
t7
t5
t11
t10
*AD5542 ONLY. CAN BE TIED PERMANENTLY LOW IF REQUIRED.
07557-
003
Figure 3. Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SY88793VKC | IC AMP POST PECL 3.3/5V 10-MSOP |
| VE-24N-IV-F3 | CONVERTER MOD DC/DC 18.5V 150W |
| DAC8408FPCZ | IC DAC 8BIT QUAD MULTIPLY 28PLCC |
| VE-24K-IV-F2 | CONVERTER MOD DC/DC 40V 150W |
| VE-24J-IV-F2 | CONVERTER MOD DC/DC 36V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5541XRZ | 制造商:Analog Devices 功能描述: |
| AD5541XRZ-RL7 | 制造商:Analog Devices 功能描述: |
| AD5542 | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V, Serial-Input Voltage-Output, 16-Bit DACs |
| AD5542A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Ultra Stable, 16-Bit ±0.5 LSB INL |
| AD5542AACPZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 V to 5.5 V, Serial-Input, Voltage-Output, 16-/12-Bit nanoDACs in LFCSP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。