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參數(shù)資料
型號(hào)： AD5542LR
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/20頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT SERIAL-IN 14-SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源： High Precision Digital-to-Analog Conversion Using the 16-Bit AD5542/1, ADR421, and AD8628 (CN0079)
How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 1µs
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 825µW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 14-SOICN
包裝： 管件
輸出數(shù)目和類型： 1 電壓，單極；1 電壓，雙極
采樣率（每秒）： 1.5M
AD5541/AD5542
Data Sheet
Rev. F | Page 6 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT 1
AGND
2
REF
3
CS
4
VDD
8
DGND
7
DIN
6
SCLK
5
AD5541
TOP VIEW
(Not to Scale)
07557-
004
Figure 4. AD5541 Pin Configuration
Table 5. AD5541 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
V
OUT
Analog Output Voltage from the DAC.
2
AGND
Ground Reference Point for Analog Circuitry.
3
REF
Voltage Reference Input for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD.
4
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
5
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
6
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
7
DGND
Digital Ground. Ground reference for digital circuitry.
8
V
DD
Analog Supply Voltage, 5 V ± 10%.
07557-
005
RFB
1
VOUT 2
AGNDF
3
AGNDS
4
VDD
14
INV
13
DGND
12
LDAC
11
REFS
5
DIN
10
REFF
6
NC
9
CS
7
SCLK
8
NC = NO CONNECT
AD5542
TOP VIEW
(Not to Scale)
Figure 5. AD5542 Pin Configuration
Table 6. AD5542 Pin Function Descriptions
Pin No.
Mnemonic
Description
1
RFB
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
2
V
OUT
Analog Output Voltage from the DAC.
3
AGNDF
Ground Reference Point for Analog Circuitry (Force).
4
AGNDS
Ground Reference Point for Analog Circuitry (Sense).
5
REFS
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD.
6
REFF
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from 2 V to V
DD.
7
CS
Logic Input Signal. The chip select signal is used to frame the serial data input.
8
SCLK
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40% and 60%.
9
NC
No Connect.
10
DIN
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
11
LDAC
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
12
DGND
Digital Ground. Ground reference for digital circuitry.
13
INV
Connected to the Internal Scaling Resistors of the DAC. Connect the INV pin to external op amps inverting input in
bipolar mode.
14
V
DD
Analog Supply Voltage, 5 V ± 10%.
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