參數(shù)資料
型號(hào)： AD5545BRUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 3/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 16BIT DUAL SRL IN 16TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 500ns
位數(shù)： 16
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 單電源
功率耗散（最大）： 55µW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 管件
輸出數(shù)目和類型： 2 電流，單極；2 電流，雙極
采樣率（每秒）： 2M
產(chǎn)品目錄頁(yè)面： 783 (CN2011-ZH PDF)
Data Sheet
AD5545/AD5555
Rev. G | Page 11 of 24
Table 7. AD5545 Control Logic Truth Table1, 2
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
X
H
X
No effect
Latched
L
H
X
No effect
Latched
L
+
H
X
Shift register data advanced one bit
Latched
L
H
X
No effect
Latched
+
L
H
X
No effect
Selected DAC updated
with current SR current
Latched
H
X
L
H
X
No effect
Latched
Transparent
H
X
H
X
No effect
Latched
H
X
+
H
X
No effect
Latched
H
X
H
L
0
No effect
Latched data = 0x0000
H
X
H
L
H
No effect
Latched data = 0x8000
1 SR = shift register,
+ = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
Table 8. AD5555 Control Logic Truth Table1, 2
CS
CLK
LDAC
RS
MSB
Serial Shift Register Function
Input Register Function
DAC Register
H
X
H
X
No effect
Latched
L
H
X
No effect
Latched
L
+
H
X
Shift register data advanced one bit
Latched
L
H
X
No effect
Latched
+
L
H
X
No effect
Selected DAC updated
with current SR current
Latched
H
X
L
H
X
No effect
Latched
Transparent
H
X
H
X
No effect
Latched
H
X
+
H
X
No effect
Latched
H
X
H
L
0
No effect
Latched data = 0x0000
H
X
H
L
H
No effect
Latched data = 0x2000
1 SR = shift register,
+ = positive logic transition, and X = don’t care.
2 At power-on, both the input register and the DAC register are loaded with all 0s.
POWER-UP SEQUENCE
It is recommended to power-up VDD and ground prior to any
reference voltages. The ideal power-up sequence is AGNDx,
DGND, VDD, VREFx, and digital inputs. A noncompliance
power-up sequence can elevate reference current, but the device
will resume normal operation once VDD is powered.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The input leads should be as direct as possible
with a minimum conductor length. Ground paths should have
low resistance and low inductance.
Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with 0.01 μF to 0.1 μF disc or
chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or
electrolytic capacitors should also be applied at VDD to minimize
any transient disturbance and to filter any low frequency ripple
(see Figure 20). Users should not apply switching regulators for
VDD due to the power supply rejection ratio degradation over
frequency.
AD5545/
AD5555
VDD
AGNDX
DGND
02918- 0- 008
C1
+
C2
10
F
0.1
F
Figure 20. Power Supply Bypassing and Grounding Connection
GROUNDING
The DGND and AGNDx pins of the AD5545/AD5555 refer to the
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 20).
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