- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8618 > AD5546BRU-REEL7 (Analog Devices Inc)IC DAC 16BIT PAR IN 28-TSSOP TR PDF資料下載
參數(shù)資料
| 型號： | AD5546BRU-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT PAR IN 28-TSSOP TR |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計資源： | Precision, Unipolar, Inverting Conversion Using AD5546/56 DAC (CN0022) Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024) Precision, Unipolar, Noninverting Configuration for the AD5546/56 DAC (CN0023) Precision, AC Reference Signal Attenuator Using AD5546/56 Multiplying DAC (CN0025) |
| 標準包裝： | 1,000 |
| 設(shè)置時間： | 500ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 55µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 2M |
Data Sheet
AD5546/AD5556
Rev. D | Page 11 of 20
DIGITAL SECTION
The AD5546/AD5556 have 16-/14-bit parallel inputs. The devices are double buffered with 16-/14-bit registers. The double-buffered
feature allows the update of several AD5546/AD5556 simultaneously. For the AD5546, the input register is loaded directly from a 16-bit
controller bus when the WR pin is brought low. The DAC register is updated with data from the input register when LDAC is brought
high. Updating the DAC register updates the DAC output with the new data (see Figure 17). To make both registers transparent, tie WR
low and LDAC high. The asynchronous RS pin resets the part to zero scale if the MSB pin = 0 and to midscale if the MSB pin = 1.
Table 5. AD5546 Parallel Input Data Format
MSB
LSB
Bit Position
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 6. AD5556 Parallel Input Data Format
MSB
LSB
Bit Position
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
Data Word
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Table 7. Control Inputs
RS
WR
LDAC
Register Operation
0
Reset output to 0, with MSB pin = 0 and to midscale with MSB pin = 1.
1
0
Load input register with data bits.
1
Load DAC register with the contents of the input register.
1
0
1
Input and DAC registers are transparent.
1
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register on
the falling edge of the pulse and then loaded into the DAC register on the rising edge of the pulse.
1
0
No register operation.
1
X = don’t care.
ESD PROTECTION CIRCUITS
All logic input pins contain back-biased ESD protection Zeners
a result, the voltage level of the logic input should not be greater
than the supply voltage.
03810-
020
5k
DIGITAL
INPUTS
DGND
VDD
Figure 18. Equivalent ESD Protection Circuits
AMPLIFIER SELECTION
In addition to offset voltage, the bias current is important in op
amp selection for precision current output DACs. An input bias
current of 30 nA in the op amp contributes to 1 LSB in the
AD5546’s full-scale error. The OP1177 and AD8628 op amps
are good candidates for the I-V conversion.
REFERENCE SELECTION
The initial accuracy and the rated output of the voltage refer-
ence determine the full span adjustment. The initial accuracy is
usually a secondary concern in precision because it can be
trimmed. Figure 23 shows an example of a trimming circuit.
The zero scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V ref-
erence with a TC of 5 ppm/oC means that the output changes by
25 V per degree Celsius. As a result, the reference that operates
at 55oC contributes an additional 750 V full-scale error.
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means that the output may change by ±250 V over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LTC1541CMS8#PBF | IC OPAMP/COMP/REF MICRPWR 8MSOP |
| VE-2TK-IV-F3 | CONVERTER MOD DC/DC 40V 150W |
| LTC1541CMS8 | IC OPAMP/COMP/REF MICRPWR 8MSOP |
| LTC1542IDD#TR | IC OPAMP/COMP/REF MICROPWR 8-DFN |
| VE-2TK-IV-F2 | CONVERTER MOD DC/DC 40V 150W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5546BRUZ | 功能描述:IC DAC 16BIT PARALL IN 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5546BRUZ | 制造商:Analog Devices 功能描述:16BIT DAC PARALLEL O/P SMD 5546 |
| AD5546BRUZ-REEL7 | 功能描述:IC DAC 16BIT PARALL IN 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:47 系列:- 設(shè)置時間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
| AD5546CRUZ | 功能描述:IC DAC 16BIT PAR 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標準包裝:1 系列:- 設(shè)置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD5546CRUZ-REEL7 | 功能描述:IC DAC 16BIT PAR 28TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓模塊:Data Converter Fundamentals DAC Architectures 標準包裝:750 系列:- 設(shè)置時間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
發(fā)布緊急采購，3分鐘左右您將得到回復。