- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄8968 > AD5547BRUZ (Analog Devices Inc)IC DAC 16BIT DUAL 38-TSSOP PDF資料下載
參數(shù)資料
| 型號(hào)： | AD5547BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT DUAL 38-TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 設(shè)計(jì)資源： | Precision, Unipolar, Inverting Conversion Using AD5547/57 DAC (CN0026) Precision, Unipolar, Noninverting Configuration for the AD5547/57 DAC (CN0027) Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028) |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 設(shè)置時(shí)間： | 500ns |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 55µW |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 38-TSSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 2M |
| 產(chǎn)品目錄頁面： | 783 (CN2011-ZH PDF) |
Data Sheet
AD5547/AD5557
Rev. D | Page 13 of 20
DIGITAL SECTION
The AD5547/AD5557 have 16-/14-bit parallel inputs. The devices
are double buffered with 16-/14-bit registers. The double buffered
feature allows the simultaneous update of several AD5547s/
AD5557s. For the AD5547, the input register is loaded directly
from a 16-bit controller bus when WR is brought low. The DAC
register is updated with data from the input register when LDAC
is brought high. Updating the DAC register updates the DAC
output with the new data (see Figure 18). To make both registers
transparent, tie WR low and LDAC high. The asynchronous RS
pin resets the part to zero scale if MSB = 0 and to midscale if
MSB = 1.
ESD Protection Circuits
All logic input pins contain back-biased ESD protection Zeners
As a result, the voltage level of the logic input should not be
greater than the supply voltage.
5k
DIGITAL
INPUTS
DGND
VDD
04452-
026
Figure 19. Equivalent ESD Protection Circuits
Amplifier Selection
In addition to offset voltage, the bias current is important in
op amp selection for precision current output DACs. A 30 nA
input bias current in the op amp contributes to 1 LSB in the
amps are good candidates for the I-to-V conversion.
Reference Selection
The initial accuracy and rated output of the voltage reference
determine the full-span adjustment. The initial accuracy of
the reference is usually a secondary concern because it can be
trimmed. Figure 25 shows an example of a trimming circuit.
The zero-scale error can also be minimized by standard op amp
nulling techniques.
The voltage reference temperature coefficient (TC) and long-
term drift are primary considerations. For example, a 5 V
reference with a TC of 5 ppm/°C means the output changes by
25 V/°C. As a result, a reference operating at 55°C contributes
an additional 750 V full-scale error.
Similarly, the same 5 V reference with a ±50 ppm long-term
drift means the output may change by ±250 V over time.
Therefore, it is practical to calibrate a system periodically to
maintain its optimum precision.
PCB LAYOUT, POWER SUPPLY BYPASSING, AND
GROUND CONNECTIONS
It is a good practice to employ a compact, minimum lead length,
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error.
It is also essential to bypass the power supply with quality
capacitors for optimum stability. Supply leads to the device
should be bypassed with 0.01 F to 0.1 F disc or chip ceramic
capacitors. Low ESR 1 F to 10 F tantalum or electrolytic
capacitors should also be applied at the supply in parallel with
the ceramic capacitor to minimize transient disturbance and
filter out low frequency ripple.
DGND terminal should be joined with the AGND terminal at
a single point. Figure 20 illustrates the basic supply bypassing
configuration and AGND/DGND connection for the
VDD
AGND
DGND
C1
C2
5V
+
–
1F
0.1F
04452-
015
AD5547/AD5557
Figure 20. Power Supply Bypassing
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VE-20W-MY-F4 | CONVERTER MOD DC/DC 5.5V 50W |
| VE-20V-MY-F4 | CONVERTER MOD DC/DC 5.8V 50W |
| VE-20V-MY-F2 | CONVERTER MOD DC/DC 5.8V 50W |
| AD5547CRUZ | IC DAC 16BIT PAR DUAL 38TSSOP |
| VE-20T-MY-F4 | CONVERTER MOD DC/DC 6.5V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD5547CRUZ | 功能描述:IC DAC 16BIT PAR DUAL 38TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD5547CRUZ-REEL7 | 功能描述:IC DAC 16BIT PAR DUAL 38TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD5547-EP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual-Current Output, Parallel Input |
| AD5547SRU-EP | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual-Current Output, Parallel Input |
| AD5551 | 制造商:AD 制造商全稱:Analog Devices 功能描述:5 V, Serial-Input Voltage-Output, 14-Bit DACs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。