參數(shù)資料
型號(hào)： AD5554BRSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 0K
描述： IC DAC 14BIT QUAD 5V 28-SSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 2µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 雙 ±
功率耗散（最大）： 1.25mW
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 管件
輸出數(shù)目和類(lèi)型： 4 電流，單極；4 電流，雙極
產(chǎn)品目錄頁(yè)面： 783 (CN2011-ZH PDF)
Data Sheet
AD5544/AD5554
Rev. G | Page 19 of 24
APPLICATIONS INFORMATION
The AD5544/AD5554 are, inherently, two-quadrant multiplying
DACs. That is, they can be easily set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.
In some applications, it may be necessary to generate the full
four-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external ampli-
fier (A2) configured as a summing amplifier (see Figure 27).
A2
A1
ONE CHANNEL
AD5544
IOUTX
RFBX
VREFX
VDD
VSS
AGNDF
AGNDX
VOUT
10k
10k
5k
AD588
VREF
10V
DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.
–10V < VOUT < +10V
00943-0-033
Figure 27. Four-Quadrant Multiplying Application Circuit
In this circuit, the first and second amplifiers (A1 and A2)
provide a total gain of 2, which increases the output voltage span
to 20 V. Biasing the external amplifier with a 10 V offset from
the reference voltage results in a full four-quadrant multiplying
circuit. The transfer equation of this circuit shows that both
negative and positive output voltages are created as the input
data (D) is incremented from code zero (VOUT = 10 V) to
midscale (VOUT = 0 V) to full scale (VOUT = 10 V).
(
)
5544
AD
the
for
1
768
,
32
REF
OUT
V
D
V
×
(3)
(
)
5554
AD
the
for
1
8192
REF
OUT
V
D
V
×
(4)
REFERENCE SELECTION
When selecting a reference for use with the AD55xx series
of current output DACs, pay attention to the output voltage,
temperature coefficient specification of the reference. Choosing
a precision reference with a low output temperature coefficient
minimizes error sources. Table 10 lists some of the references
available from Analog Devices, Inc., that are suitable for use
with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
Because of the code-dependent output resistance of the DAC,
the input offset voltage of an op amp is multiplied by the variable
gain of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed upon the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, can cause the DAC to be
nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output because of the bias current flowing in the
feedback resistor, RFB.
Common-mode rejection of the op amp is important in voltage-
switching circuits because it produces a code-dependent error
at the voltage output of the circuit.
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-switching
DAC circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, minimize capacitance
at the VREF node (the voltage output node in this application) of
the DAC. This is done by using low input capacitance buffer
amplifiers and careful board design.
Analog Devices offers a wide range of amplifiers for both precision
dc and ac applications, as listed in Table 11 and Table 12.
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