參數(shù)資料
型號(hào): AD5556CRU
廠商: Analog Devices Inc
文件頁(yè)數(shù): 18/20頁(yè)
文件大?。?/td> 0K
描述: IC DAC 14BIT PARALL IN 28-TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Precision, Unipolar, Inverting Conversion Using AD5546/56 DAC (CN0022)
Precision, Bipolar Configuration for the AD5546/56 DAC (CN0024)
Precision, Unipolar, Noninverting Configuration for the AD5546/56 DAC (CN0023)
Precision, AC Reference Signal Attenuator Using AD5546/56 Multiplying DAC (CN0025)
標(biāo)準(zhǔn)包裝: 50
設(shè)置時(shí)間: 500ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 125°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 28-TSSOP
包裝: 管件
輸出數(shù)目和類(lèi)型: 1 電流,單極;1 電流,雙極
采樣率(每秒): 2M
Data Sheet
AD5546/AD5556
Rev. D | Page 7 of 20
Pin No.
Mnemonic
Description
13
REF
DAC Reference Input in Two-Quadrant Mode and R2 Terminal in Four-Quadrant Mode. In two-quadrant mode, this
pin is the reference input with constant input resistance vs. code. In four-quadrant mode, this pin is driven by the
external reference amplifier.
14
IOUT
DAC Current Output. Connects to the inverting node of an external op amp for I-V conversion.
15
LDAC
Digital Input Load DAC Control. The signal level must be ≤ VDD + 0.3 V.
16
WR
Write Control Digital Input in Active Low. Transfers shift-register data to the DAC register on the rising edge. The
signal level must be ≤ VDD + 0.3 V.
17
MSB
Power On Reset State. MSB = 0 resets at zero scale; MSB = 1 resets at midscale. The signal level must be
≤ VDD + 0.3 V.
18
RS
Reset in Active Low. Resets to zero scale if MSB = 0 and resets to midscale if MSB = 1. The signal level must be
≤ VDD + 0.3 V.
19
GND
Analog and Digital Grounds.
20 to 27
D13 to D6
Digital Input Data Bits[D13:D6]. The signal level must be ≤ VDD + 0.3 V.
28
VDD
Positive Power Supply Input. Specified range of operation: 2.7 V to 5.5 V.
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