參數(shù)資料
型號(hào): AD5557CRU
廠商: Analog Devices Inc
文件頁數(shù): 20/20頁
文件大?。?/td> 0K
描述: IC DAC 14BIT 2CH I OUT 38TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計(jì)資源: Precision, Unipolar, Inverting Conversion Using AD5547/57 DAC (CN0026)
Precision, Unipolar, Noninverting Configuration for the AD5547/57 DAC (CN0027)
Precision, Bipolar, Configuration for AD5547/AD5557 DAC (CN0028)
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 500ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 單電源
功率耗散(最大): 55µW
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 38-TFSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 38-TSSOP
包裝: 管件
輸出數(shù)目和類型: 2 電流,單極;2 電流,雙極
采樣率(每秒): 2M
Data Sheet
AD5547/AD5557
Rev. D | Page 9 of 20
Pin No.
Mnemonic
Function
23
RS
Active low resets both input and DAC registers. Resets to zero-scale if MSB = 0 and resets to midscale if MSB = 1.
Signal level must be ≤V
DD + 0.3 V.
24 to 28,
30 to 38
D13 to D0
Digital Input Data Bits D13 to D0. Signal level must be ≤V
DD + 0.3 V.
29
VDD
Positive Power Supply Input. The specified range of operation is 2.7 V to 5.5 V.
Table 5. Address Decoder Pins
A1
A0
Output Update
0
DAC A
0
1
None
1
0
DAC A and DAC B
1
DAC B
Table 6. Control Inputs
RS
WR
LDAC
Register Operation
0
X
Reset the output to 0 with MSB = 0; reset the output to midscale with MSB = 1.
1
0
Load the input register with data bits.
1
Load the DAC register with the contents of the input register.
1
0
1
The input and DAC registers are transparent.
1
When LDAC and WR are tied together and programmed as a pulse, the data bits are loaded into the input register
on the falling edge of the pulse and are then loaded into the DAC register on the rising edge of the pulse.
1
0
No register operation.
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