VOUT SELECT V
參數(shù)資料
型號: AD558JPZ
廠商: Analog Devices Inc
文件頁數(shù): 7/8頁
文件大?。?/td> 0K
描述: IC DAC 8BIT AMP/MCU 20-PLCC
產(chǎn)品培訓模塊: Data Converter Fundamentals
DAC Architectures
標準包裝: 49
系列: DACPORT®
設置時間: 800ns
位數(shù): 8
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 375mW
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 20-LCC(J 形引線)
供應商設備封裝: 20-PLCC(9x9)
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極;1 電壓,雙極
采樣率(每秒): *
AD558
REV. A
–7–
OUTPUT
AMP
16
15
14
13
AGND
VOUT SELECT
VOUT SENSE
VOUT
–V
0.5mA
b. 0 V to 10 V Output Range
Figure 11. Offset Connection Diagrams
INTERFACING THE AD558 TO MICROPROCESSOR
DATA BUSES
The AD558 is configured to act like a “write only” location in
memory that may be made to coincide with a read only memory
location or with a RAM location. The latter case allows data
previously written into the DAC to be read back later via the
RAM. Address decoding is partially complete for either ROM
or RAM. Figure 12 shows interfaces for three popular micropro-
cessor systems.
ADDRESS BUS
DATA BUS
6800
VMA
φ2
R/W
AD558
VOUT
DB0–DB7
16
8
CE
CS
ADDRESS
DECODER
16
R/W
→ CE
GATED DECODED ADDRESS
→ CS
a. 6800/AD558 Interface
ADDRESS BUS
DATA BUS
8080A
AD558
VOUT
DB0–DB7
16
8
CE
CS
ADDRESS SELECT
PULSE LOGIC
16
MEMW
→ CE
DECODED ADDRESS SELECT PULSE
→ CS
b. 8080A/AD558 Interface
ADDRESS BUS
DATA BUS
1802
AD558
VOUT
DB0–DB7
8
CE
CS
ADDRESS
LATCH
&
DECODE
8
MWR
CDP 1802: MWR
→ CE
DECODED ADDRESS SELECT PULSE
→ CS
TPA
MA 0 – 7
c. 1802/AD558 Interface
Figure 12. Interfacing the AD558 to Microprocessors
Performance (typical @ +25 C, V
CC
+5 V to +15 V unless otherwise noted)
0
LSB
1.75
1.50
1.25
1.00
0.75
0.50
0.25
–0.25
–0.50
–0.75
–1.00
–55
–25
0
+25
+50
+75
+100
+125
oC
FULL
SCALE
ERROR
ALL AD558
AD558S, T
1LSB = 0.39% OF FULL SCALE
Figure 13. Full-Scale Accuracy vs. Temperature
Performance of AD558
0
LSB
1/2
1/4
–55
–25
0
+25
+50
+75
+100
+125
oC
ZERO
ERROR
ALL AD558
AD558S, T
1LSB = 0.39% OF FULL SCALE
–1/4
–1/2
Figure 14. Zero Drift vs. Temperature Performance
of AD558
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