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| 型號(hào)： | AD5626BRMZ-REEL7 |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC NANO 12BIT 8-MSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | nanoDAC™ |
| 設(shè)置時(shí)間： | 16µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 12.5mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸出數(shù)目和類(lèi)型： | 1 電壓，單極；1 電壓，雙極 |
| 采樣率（每秒）： | * |
| 其它名稱(chēng)： | AD5626BRMZ-REEL7DKR |
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AD5626
Rev. A | Page 10 of 20
THEORY OF OPERATION
The AD5626 is a complete, ready-to-use, 12-bit digital-to-analog
converter (DAC). It contains a voltage-switched, 12-bit, laser-
trimmed DAC, a curvature-corrected band gap reference, a
rail-to-rail output op amp, a DAC register, and a serial data
input register. The serial data interface consists of an SCLK,
serial data in (SDIN), and a load strobe (LDAC). This basic
3-wire interface offers maximum flexibility for interface to the
widest variety of serial data input loading requirements. In
addition, a CS select is provided for multiple packaging loading
and a power-on-reset CLR pin to simplify start or periodic resets.
DAC SECTION
The DAC is a 12-bit voltage mode device with an output that
swings from the GND potential to the 2.5 V internal band gap
voltage. It uses a laser trimmed, rail-to-rail ladder which is
switched by N-channel MOSFETs. The output voltage of the
DAC has a constant resistance independent of digital input
code. The DAC output internally connects to the rail-to-rail
output op amp.
AMPLIFIER SECTION
A low power consumption, precision amplifier buffers the DAC
output. This amplifier contains a differential PNP pair input
stage that provides low offset voltage and low noise, as well as
the ability to amplify the zero-scale DAC output voltages.
The rail-to-rail amplifier is configured with a gain of 1.6384
(= 4.095 V/2.5 V) to set the 4.095 V full-scale output (1 mV/LSB).
See Figure 23 for an equivalent circuit schematic of the analog
section.
06
757
-02
3
2R
R2
R
2R
R
R1
VOUT
BUFFER
BAND GAP
REFERENCE
2.5V
SPDT
N-CHANNEL FET
SWITCHES
RAIL-TO-RAIL
OUTPUT
AMPLIFIER
AV = 1.638
(= 4.095V/2.5V)
VOLTAGE SWITCHED 12-BIT
RAIL-TO-RAIL CONVERTER
Figure 23. Equivalent AD5626 Schematic of Analog Section
The op amp has a 16 μs typical settling time to 0.01%. There are
slight differences in settling time for negative slewing signals vs.
positive slewing signals. See the oscilloscope photos in the
Typical Performance Characteristics section of this data sheet.
OUTPUT SECTION
The rail-to-rail output stage of this amplifier is designed to
provide precision performance when operating near either
power supply.
06
75
7-
02
4
P-CH
VDD
VOUT
AGND
N-CH
Figure 24. Equivalent Analog Output Circuit
Figure 24 shows an equivalent output schematic of the rail-to-
rail amplifier with its N-channel pull-down FETs that pull an
output load directly to GND. The output sourcing current is
provided by a P-channel pull-up device that can supply GND
terminated loads, especially at the low supply tolerance values
swing performance near ground and full-scale as a function of
load. In addition to resistive load driving capability, the amplifier
has also been carefully designed and characterized for up to
500 pF capacitive load driving capability.
POWER SUPPLY
The very low power consumption of the AD5626 is a direct
result of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors, good analog accuracy is achieved.
For power consumption sensitive applications, it is important
to note that the internal power consumption of the AD5626
is strongly dependent on the actual logic input voltage levels
present on the SDIN, CS, LDAC, and CLR pins. Because these
inputs are standard CMOS logic structures, they contribute
static power dissipation dependent on the actual driving
Logic VOH and Logic VOL voltage levels. The graph in
shows the effect on total AD5626 supply current as a function
of the actual value of input logic voltage. Consequently, use of
CMOS logic vs. TTL minimizes power dissipation in the static
state. A VIL = 0 V on the SDIN,
CS, and CLR pins provides the
lowest standby power dissipation of 2.5 mW (500 μA × 5 V).
As with any analog system, it is recommended that the AD5626
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection vs. frequency
performance. This should be taken into account when using higher
frequency, switched mode power supplies with ripple frequencies
of 100 kHz and higher.
One advantage of the rail-to-rail output amplifier used in the
AD5626 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
4.75 V to 5.25 V. If reduced linearity and source current capa-
bility near full scale can be tolerated, operation of the AD5626
is possible down to 4.3 V. The minimum operating supply
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| AD5627BCPZ-R2 | 功能描述:IC DAC 12BIT DUAL 10-LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:nanoDAC™ 產(chǎn)品培訓(xùn)模塊:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色產(chǎn)品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 標(biāo)準(zhǔn)包裝:91 系列:- 設(shè)置時(shí)間:4µs 位數(shù):10 數(shù)據(jù)接口:MICROWIRE?，串行，SPI? 轉(zhuǎn)換器數(shù)目:8 電壓電源:單電源 功率耗散（最大）:2.7mW 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:14-WFDFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:14-DFN-EP（4x3） 包裝:管件 輸出數(shù)目和類(lèi)型:8 電壓，單極 采樣率（每秒）:* |
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