參數(shù)資料
型號(hào)： AD565AJRZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 12/12頁(yè)
文件大?。?/td> 0K
描述： IC DAC 12BIT MONO 250NS 28SOIC
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時(shí)間： 250ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 單電源
功率耗散（最大）： 345mW
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 1 電流，單極；1 電流，雙極
采樣率（每秒）： *
AD565A/AD566A
REV. E
–9–
CONNECTING THE AD566A FOR BUFFERED VOLTAGE
OUTPUT
The standard current-to-voltage conversion connections using an
operational amplifier are shown in Figures 4, 5, and 6 with the
preferred trimming techniques. If a low offset operational amplifier
(OP77, AD741L, OP07) is used, excellent performance can be
obtained in many situations without trimming (an op amp with
less than 0.5 mV max offset voltage should be used to keep offset
errors below 1/2 LSB). If a 50
fixed resistor is substituted for the
100
trimmer, unipolar zero typically is within ±1/2 LSB (plus op
amp offset), and full-scale accuracy is within 0.1% (0.25% max).
Substituting a 50
resistor for the 100 bipolar offset trimmer
gives a bipolar zero error typically within
±2 LSB (0.05%).
The AD509 is recommended for buffered voltage-output
applications that require a settling time to
±1/2 LSB of 1 s. The
feedback capacitor is shown with the optimum value for each
application; this capacitor is required to compensate for the
25 pF DAC output capacitance.
FIGURE 4. UNIPOLAR CONFIGURATION
This configuration provides a unipolar 0 V to 10 V output range.
In this mode, the bipolar terminal, Pin 7, should be grounded if not
used for trimming.
100k
+15V
–15V
R1
50k
19.95k
20k
0.5mA
IREF
DAC
IOUT =
4
IREF
CODE
AD566A
9.95k
5k
8k
IO
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–VEE
REF
GND
BIPOLAR OFF
5k
CODE
INPUT
LSB
MSB
R2
100
10pF
AD509
2.4k
100
10V EREF
AD561
+V
REF
IN
Figure 4. 0 V to 10 V Unipolar Voltage Output
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R1, until the output
reads 0.000 V (1 LSB = 2.44 mV). In most cases, this trim is
not needed, but Pin 7 should then be connected to Pin 12.
STEP II . . . GAIN ADJUST
Turn all bits ON and adjust 100
gain trimmer, R2, until the
output is 9.9976 V. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 V.) If a 10.2375 V full scale is desired
(exactly 2.5 mV/bit), insert a 120
resistor in series with the
gain resistor at Pin 10 to the op amp output.
FIGURE 5. BIPOLAR CONFIGURATION
This configuration provides a bipolar output voltage from
–5.000 V to +4.9976 V, with positive full scale occurring with
all bits ON (all 1s).
19.95k
20k
0.5mA
IREF
DAC
IOUT =
4
IREF
CODE
AD566A
9.95k
5k
8k
IO
20V SPAN
10V SPAN
DAC
OUT
POWER
GND
–VEE
REF
GND
BIPOLAR OFF
5k
CODE
INPUT
LSB
MSB
R2
100
10pF
AD509
2.4k
10V EREF
AD561
+V
REF
IN
R1
100
Figure 5.
±5 V Bipolar Voltage Output
STEP I . . . OFFSET ADJUST
Turn OFF all bits. Adjust 100
trimmer R1 to give –5.000
output V.
STEP II . . . GAIN ADJUST
Turn ON all bits. Adjust 100
gain trimmer R2 to give a read-
ing of +4.9976 V.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
an op amp trim is unnecessary unless the untrimmed offset drift
of the op amp is excessive.
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