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參數(shù)資料
| 型號： | AD5664BRMZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QUAD 10-MSOP |
| 產(chǎn)品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1,000 |
| 系列： | nanoDAC™ |
| 設置時間： | 4µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | 223k |
| 配用： | EVAL-AD5664REBZ-ND - BOARD EVALUATION FOR AD5664R |
AD5624/AD5664
Rev. 0 | Page 18 of 24
LDAC FUNCTION
The AD5624/AD5664 DACs have double-buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The input registers are connected directly to the input
shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The
DAC registers contain the digital code used by the resistor
strings.
The double-buffered interface is useful if the user requires
simultaneous updating of all DAC outputs. The user can write
to three of the input registers individually and then write to the
remaining input register and update all DAC registers, the
outputs update simultaneously. Command 010 is reserved for
this software LDAC.
Access to the DAC registers is controlled by the LDAC
function. The LDAC registers contain two modes of operation
for each DAC channel. The DAC channels are selected by
setting the bits of the 4-bit LDAC register (DB3, DB2, DB1, and
DB0). Command 110 is reserved for setting up the LDAC
register. When the LDAC bit register is set low, the
corresponding DAC registers are latched and the input
registers can change state without affecting the contents of the
DAC registers. When the LDAC bit register is set high,
however, the DAC registers become transparent and the
contents of the input registers are transferred to them on the
falling edge of the 24th SCLK pulse. This is equivalent to having
an LDAC hardware pin tied permanently low for the selected
DAC channel, that is, synchronous update mode. See Table 12
for the LDAC register mode of operation. See Table 13 for
contents of the input shift register during the LDAC register set-
up command.
This flexibility is useful in applications where the user wants to
update select channels simultaneously, while the rest of the
channels update synchronously.
Table 12.
LDAC Register Mode of Operation
Load DAC Register
LDAC Bits
(DB3 to DB0)
LDAC Mode of Operation
0
Normal operation (default), DAC register
update is controlled by write command.
1
The DAC registers are updated after new
data is read in on the falling edge of the
24th SCLK pulse.
Table 13. 24-Bit Input Shift Register Contents for LDAC Setup Command for the AD5624/AD5664
DB23 to
DB22
(MSB)
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to
DB4
DB3
DB2
DB1
DB0
(LSB)
x
1
0
x
DacD
DacC
DacB
DacA
Don’t Care
Command bits (C2 to C0)
Address bits (A3 to A0); don’t care
Don’t
cares
Set bit to 0 or 1 for required mode of
operation on respective channel
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