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| 型號： | AD5669RACPZ-2-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT I2C/SRL 16LFCSP-WQ |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 系列： | denseDAC |
| 設(shè)置時(shí)間： | 2.5µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-WQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 16-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 166k |
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AD5629R/AD5669R
Data Sheet
Rev. D | Page 22 of 32
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages
on its output, which gives an output range of 0 V to VDD. The
amplifier is capable of driving a load of 2 kΩ in parallel with
1000 pF to GND. The source and sink capabilities of the output
amplifier can be seen in Figure 2
5 and Figure 26. The slew rate
is 1.5 V/μs with a to scale settling time of 10 μs.
SERIAL INTERFACE
interfaces (refer to The I2C-Bus Specification, Version 2.1,
January 2000, available from Philips Semiconductor). The
device under the control of a master device. See Figure 2 for a
timing diagram of a typical write sequence.
The AD5629R/AD5669R support standard (100 kHz) and fast
(400 kHz) modes. High speed operation is only available on
selected models. See the Ordering Guide for a full list of
models. Support is not provided for 10-bit addressing and
general call addressing.
The AD5629R/AD5669R each have a 7-bit slave address.
The parts have a slave address whose five MSBs are 10101,
and the two LSBs are set by the state of the A0 address pin,
which determines the state of the A0 and A1 address bits.
The facility to make hardwired changes to the A0 pin allows the
user to incorporate up to three of these devices on one bus, as
outlined in Table 7.
Table 7. ADDR Pin Settings
A0 Pin Connection
A1
A0
VDD
0
NC
1
0
GND
1
The 2-wire serial bus protocol operates as follows:
1.
The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the ninth clock pulse (this is
termed the acknowledge bit). At this stage, all other devices
on the bus remain idle while the selected device waits for
data to be written to or read from its shift register.
2.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during
the low period of SCL and remain stable during the high
period of SCL.
3.
When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master brings the SDA line low
before the 10th clock pulse and then high during the 10th
clock pulse to establish a stop condition.
WRITE OPERATION
When writing to the AD5629R/AD5669R, the user must begin
with a start command followed by an address byte (R/W = 0),
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The AD5629R/AD5669R require two
bytes of data for the DAC and a command byte that controls
various DAC functions. Three bytes of data must, therefore, be
written to the DAC, the command byte followed by the most
significant data byte and the least significant data byte, as shown in
Figure 51. After these data bytes are acknowledged by the
READ OPERATION
user begins with a start command followed by an address byte
(R/W = 1), after which the DAC acknowledges that it is prepared
to transmit data by pulling SDA low. Two bytes of data are then
read from the DAC, which are both acknowledged by the master as
shown in Figure 52. A stop condition follows.
FRAME 2
COMMAND BYTE
FRAME 1
SLAVE ADDRESS
19
9
1
SCL
START BY
MASTER
ACK. BY
AD5629R/AD5669R
ACK. BY
AD5629R/AD5669R
SDA
R/W
DB23
A0
A1
1
0
1
0
DB22 DB21
DB20
DB19 DB18
DB17
DB16
19
9
1
ACK. BY
AD5629R/AD5669R
ACK. BY
AD5629R/AD5669R
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
FRAME 3
MOST SIGNIFICANT
DATA BYTE
STOP BY
MASTER
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14
DB13 DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
08
81
9-
0
48
Figure 51. I2C Write Operation
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