V
參數(shù)資料
型號： AD5678BRUZ-1REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 2/28頁
文件大小： 0K
描述： IC DAC 12/16BIT SPI/SRL 14TSSOP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
設(shè)置時間： 6µs
位數(shù)： 12，16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： 95k
AD5678
Rev. C | Page 10 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
05
29
9-
0
03
1
2
3
4
5
6
7
AD5678
VDD
VOUTA
VOUTC
VREFIN/VREFOUT
VOUTG
VOUTE
14
13
12
11
10
9
8
DIN
GND
VOUTB
VOUTH
VOUTF
VOUTD
SCLK
TOP VIEW
(Not to Scale)
SYNC
Figure 3. 14-Lead TSSOP (RU-14)
05
29
9-
0
04
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SYNC
VDD
VOUTA
VOUTG
VOUTE
VOUTC
LDAC
DIN
GND
VOUTB
VOUTH
VREFIN/VREFOUT
CLR
VOUTF
VOUTD
SCLK
AD5678
TOP VIEW
(Not to Scale)
Figure 4. 16-Lead TSSOP (RU-16)
Table 6. Pin Function Descriptions
Pin No.
14-Lead
TSSOP
16-Lead
TSSOP
Mnemonic
Description
N/A
1
LDAC
Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be
tied permanently low.
1
2
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When
SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register.
Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before
the 32nd falling edge, the rising edge of SYNC acts as an interrupt and the write sequence is
ignored by the device.
2
3
VDD
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should
be decoupled with a 10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
3
4
VOUTA
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
11
13
VOUTB
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
4
5
VOUTC
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
10
12
VOUTD
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
7
8
VREFIN/VREFOUT
The AD5678 has a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is
the reference input pin. The default for this pin is as a reference input.
N/A
9
CLR
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC
pulses are ignored. When CLR is activated, the input register and the DAC register are
updated with the data contained in the CLR code register—zero, midscale, or full scale.
Default setting clears the output to 0 V.
5
6
VOUTE
Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.
9
11
VOUTF
Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.
6
7
VOUTG
Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.
8
10
VOUTH
Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.
12
14
GND
Ground Reference Point for All Circuitry on the Part.
13
15
DIN
Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on
the falling edge of the serial clock input.
14
16
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
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