參數(shù)資料
型號： AD568KQ
廠商： Analog Devices Inc
文件頁數(shù)： 7/14頁
文件大?。?/td> 0K
描述： IC DAC 12BIT HS MONO 35NS 24CDIP
產(chǎn)品培訓模塊： Data Converter Fundamentals
DAC Architectures
標準包裝： 1
設置時間： 35ns
位數(shù)： 12
數(shù)據(jù)接口： 并聯(lián)
轉換器數(shù)目： 1
電壓電源： 雙 ±
工作溫度： 0°C ~ 70°C
安裝類型： 通孔
封裝/外殼： 24-CDIP（0.300"，7.62mm）
供應商設備封裝： 24-CDIP
包裝： 管件
輸出數(shù)目和類型： 1 電流，單極；1 電流，雙極；1 電壓，單極；1 電壓，雙極
采樣率（每秒）： *
Model
AD568J
AD568K
AD568S
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Units
RESOLUTION
12
Bits
ACCURACY
1
Linearity
–1/2
+1/2
–1/4
+1/4
–1/2
+1/2
LSB
TMIN to TMAX
–3/4
+3/4
–1/2
+1/2
–3/4
+3/4
LSB
Differential Nonlinearity
–1
+1
–1/2
+1/2
–1
+1
LSB
TMIN to TMAX
–1
+1
–1
+ 1
–1
LSB
Monotonicity
GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE
Unipolar Offset
–0.2
+0.2
*
% of FSR
Bipolar Offset
–1.0
+1.0
*
% of FSR
Bipolar Zero
–0.2
+0.2
*
% of FSR
Gain Error
–1.0
+1.0
*
% of FSR
TEMPERATURE COEFFICIENTS
2
Unipolar Offset
–5
+5
–3
+3
–5
+5
ppm of FSR/
°C
Bipolar Offset
–30
+30
–20
+20
–30
+30
ppm of FSR/
°C
Bipolar Zero
–15
+15
ppm of FSR/
°C
Gain Drift
–50
+50
–30
+30
–50
+50
ppm of FSR/
°C
Gain Drift (IOUT)
–150
+150
*
ppm of FSR/
°C
DATA INPUTS
Logic Levels (TMIN to TMAX)
VIH
2.0
7.0
**
V
VIL
0.0
0.8
**
V
Logic Currents (TMIN to TMAX)
IIH
–10
0
+10
**
*
**
A
IIL
–0.5
–60
–100
*
–100
–200
A
VTH Pin Voltage
1.4
*
V
CODING
BINARY, OFFSET BINARY
CURRENT OUTPUT RANGES
0 to 10.24,
±5.12
mA
VOLTAGE OUTPUT RANGES
0 to 1.024,
±0.512
V
COMPLIANCE VOLTAGE
–2
+1.2
*
V
OUTPUT RESISTANCE
Exclusive of RL
160
200
240
*
Inclusive of RL
99
100
101
*
SETTLING TIME
Current to
± 0.025%
35
*
ns to 0.025% of FSR
± 0.1%
23
*
ns to 0.1% of FSR
Voltage
50
Load3, 0.512 V p-p,
to 0.025%
37
*
ns to 0.025% of FSR
to 0.1%
25
*
ns to 0.1% of FSR
to 1%
18
*
ns to 1% of FSR
75
Load3, 0.768 V p-p,
to 0.025%
40
*
ns to 0.025% of FSR
to 0.1%
25
*
ns to 0.1% of FSR
to 1%
20
*
ns to 1% of FSR
100
(Internal R
L)
3, 1.024 V p-p,
to 0.025%
50
*
ns to 0.025% of FSR
to 0.1%
38
*
ns to 0.1% of FSR
to 1%
24
*
ns to 1% of FSR
Glitch Impulse
4
350
*
pV-sec
Peak Amplitude
15
*
% of FSR
FULL-SCALE TRANSlTlON
5
10% to 90% Rise Time
11
*
ns
90% to 10% Fall Time
11
*
ns
POWER REQUIREMENTS
+13.5 V to +16.5 V
27
32
**
*
mA
–13.5 V to –16.5 V
–7
–8
**
*
mA
Power Dissipation
525
625
*
mW
PSRR
0.05
*
% of FSR/V
TEMPERATURE RANGE
Rated Specification
2
0
+70
0
+70
–55
+125
°C
Storage
–65
+150
*
°C
NOTES
*Same as AD568J.
1Measured in I
OUT mode.
2Measured in V
OUT mode, unless otherwise specified. See text for further information.
3Total Resistance. Refer to Figure 3,
4At the major carry, driven by HCMOS logic. See text for further explanation.
5Measured in V
OUT mode.
Specifications shown in boldface are tested on all production units at final electrical test.
Specifications subject to change without notice.
REV. A
–2–
(@ = +25 C, VCC, VEE =
15 V unless otherwise noted)
AD568–SPECIFICATIONS
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