TA = 25°C, unles" />
參數(shù)資料
型號: AD5724RBREZ
廠商: Analog Devices Inc
文件頁數(shù): 32/32頁
文件大?。?/td> 0K
描述: IC DAC 12BIT DSP/SRL 24TSSOP
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
設(shè)計資源: Software Configurable 12-Bit Quad Channel Unipolar/Bipolar Voltage Output Using AD5724R (CN0085)
標準包裝: 1
設(shè)置時間: 10µs
位數(shù): 12
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字,雙 ±
功率耗散(最大): 310mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm)裸露焊盤
供應(yīng)商設(shè)備封裝: 24-TSSOP 裸露焊盤
包裝: 管件
輸出數(shù)目和類型: 4 電壓,單極;4 電壓,雙極
采樣率(每秒): *
產(chǎn)品目錄頁面: 784 (CN2011-ZH PDF)
AD5724R/AD5734R/AD5754R
Rev. E | Page 9 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. Transient currents of up to
100 mA do not cause SCR latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 5.
Parameter
Rating
AVDD to GND
0.3 V to +17 V
AVSS to GND
+0.3 V to 17 V
DVCC to GND
0.3 V to +7 V
Digital Inputs to GND
0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND
0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
REFIN/REFOUT to GND
0.3 V to +5 V
VOUTx to GND
AVSS to AVDD
DAC_GND to GND
0.3 V to +0.3 V
SIG_GND to GND
0.3 V to +0.3 V
Operating Temperature Range, TA
Industrial
40°C to +85°C
Storage Temperature Range
65°C to +150°C
Junction Temperature, TJ max
150°C
24-Lead TSSOP Package
θJA Thermal Impedance
42°C/W
θJC Thermal Impedance
9°C/W
Power Dissipation
(TJ max – TA)/θJA
Lead Temperature
JEDEC industry standard
Soldering
J-STD-020
ESD (Human Body Model)
3.5 kV
ESD CAUTION
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