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參數(shù)資料
| 型號(hào)： | AD5725BRSZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT QUAD PAR 28-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 270mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | * |
Data Sheet
AD5725
Rev. C | Page 15 of 20
THEORY OF OPERATION
The AD5725 is a quad voltage output, 12-bit parallel input DAC
featuring a 12-bit data bus with readback capability. The AD5725
operates from single or dual supplies ranging from +5 V up to
±15 V. The output voltage range is set by the reference voltages
applied at the VREFP and VREFN pins.
DAC ARCHITECTURE
Each of the four DACs is a voltage switched, high impedance
(50 kΩ), R-2R ladder configuration. Each 2R resistor is driven
by a pair of switches that connect the resistor to either VREFH
or VREFL.
OUTPUT AMPLIFIERS
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 500 pF to DGND. The source and sink
capabilities of the output amplifiers can be seen in Figure 23
and Figure 24. The slew rate is 2.2 V/s with a full-scale settling
time of 10 s. The amplifiers are short-circuit protected.
Careful attention to grounding is important for accurate
operation of the AD5725. With four outputs and two references
there is potential for ground loops. Since the AD5725 has no
analog ground, the ground must be specified with respect to the
reference.
REFERENCE INPUTS
All four DACs share common positive reference (VREFP) and
negative reference (VREFN) inputs. The voltages applied to these
reference inputs set the output high and low voltage limits on all
four of the DACs. Each reference input has voltage restrictions
with respect to the other reference and to the power supplies.
VREFN can be any voltage between AVSS and VREFP 2.5 V and
VREFP can be any value between AVDD – 2.5 V and
VREFN + 2.5 V. Note that because of these restrictions, the
AD5725 references cannot be inverted (VREFN cannot be
greater than VREFP).
It is important to note that the AD5725 VREFP input both sinks
and sources current. Also, the input current of both VREFP and
VREFN are code dependent. Many references have limited current
sinking capability and must be buffered with an amplifier to
drive VREFP. The VREFN reference input has no such special
requirements.
It is recommended that the reference inputs be bypassed with
0.2 F capacitors when operating with ±10 V references. This
limits the reference bandwidth.
PARALLEL INTERFACE
See Table 7 for the digital control logic truth table. The parallel
interface consists of a 12-bit bidirectional data bus, two register
select inputs, A0 and A1, a R/W input, a chip select (CS), and a
load DAC (LDAC) input. Control of the DACs and bus
direction is determined by these inputs as shown in Table 7.
Digital data bits are labeled with the MSB defined as Data Bit 11
and the LSB as Data Bit 0. All digital pins are TTL/CMOS
compatible.
The register select inputs A0 and A1 select individual DAC
Register A (Binary Code 00) through Register D (Binary Code 11).
Decoding of the registers is enabled by the CS input. When CS
is high, no decoding takes place, and neither the writing nor the
reading of the input registers is enabled. The loading of the
second bank of registers is controlled by the asynchronous
LDAC input. By taking LDAC low while CS is high, all output
registers can be updated simultaneously. Note that the tLDW
required pulse width for updating all DACs is a minimum of
10 ns. The R/W input, when enabled by CS, controls the writing
to and reading from the input register.
DATA CODING
The AD5725 uses binary coding. The output voltage can be
calculated as follows:
(
)
4096
D
V
REFN
REFP
REFN
OUT
×
+
=
where D is the digital code in decimal.
CLR
The CLR function can be used either at power-up or at any time
during the DACs operation. The CLR function is independent
of CS. This pin is active low and sets the DAC registers to either
midscale code (0x800) for the AD5725 or zero code (0x000) for
the AD5725-1. The CLR to midscale code is most useful when
the DAC is configured for bipolar references and an output of
0 V is desired.
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